User manual

...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 207
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Figure 14.42. EBI TFT Horizontal Porch Timing
EBI_AD[15:0]
EBI_HSYNC
EBI_DATAEN
EBI_DCLK
P0
HSZ
(1, 2, 3, ...)
HORIZONTAL BACK PORCH P1
...
...
P
HSZ
HORIZONTAL FRONT PORCH
HBPORCH
(0, 1, 2, ...)
HFPORCH
(0, 1, 2, ...)
...
...
...
...
...
... ...
...
...
...
...
HSYNC
(1, 2, 3, ...)
HSYNCSTART
(0, 1, 2, ...)
The timing parameters related to the vertical timing are shown in Figure 14.43 (p. 207) . These
parameters are defined as line or EBI_HSYNC counts. The vertical porch widths are defined in the
VBPORCH and VFPORCH bitfields of the EBI_TFTVPORCH register. A porch which has its width
parameter programmed to 0 will be skipped. The width of the vertical synchronization pulse EBI_VSYNC
is programmed via the VSYNC bitfield in the EBI_TFTVPORCH register.
Figure 14.43. EBI TFT Vertical Porch Timing
LINES
EBI_HSYNC
L0
VSZ
(1, 2, 3, ...)
VERTICAL BACK PORCH L1
...
L
VSZ
VERTICAL FRONT PORCH
VBPORCH
(0, 1, 2, ...)
VFPORCH
(0, 1, 2, ...)
...
...
...
...
...
...
... ...
EBI_VSYNC
VSYNC
(1, 2, 3, ...)
The active edge of the EBI_DCLK and the other TFT related signals are by default driven off the positive
edge of the internal clock. The edges of the EBI_DCLK can also be driven off the negative edge of the
internal clock by setting the SHIFTDCLK bitfield in the EBI_TFTCTRL register to 1. The Direct Drive
engine then shifts the active DCLK edge 1/2 an internal cycle into the TFTHOLD state. Effectively the
length of TFTSETUP state is increased by 1/2 an internal cycle, whereas the length of the TFTHOLD
state is decreased by 1/2 an internal cycle. SHIFTDCLK should not be set if TFTHOLD is set to zero
cycles. The effect of the SHIFTDCLK bitfield is shown in Figure 14.44 (p. 207) and Figure 14.45 (p.
207) for a setup using the falling EBI_DCLK clock as its active edge.
Figure 14.44. EBI TFT Pixel Timing: EBI_DCLK driven off Positive Edge Internal Clock
EBI_AD[15:0]
EBI_DCLK
TFTHOLD
(0, 1, 2, ...)
PIXEL N
TFTSETUP
(0, 1, 2, ...)
INTERNAL CLOCK
Figure 14.45. EBI TFT Pixel Timing: EBI_DCLK driven off Negative Edge Internal Clock
EBI_AD[15:0]
EBI_DCLK
TFTHOLD
(1, 2, 3, ...)
PIXEL N
TFTSETUP
(0, 1, 2, ...)
INTERNAL CLOCK
(½)
(½, 1 ½, 2 ½ , ...)