User manual

...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 193
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Figure 14.29. EBI NAND Flash Data Input Timing
EBI_AD[y] = NAND CLE
WRSETUP
(0, 1, 2, ...)
WRSTRB
(1, 2, 3, ...)
GPIO or EBI_CSn = NAND CEn
EBI_NANDWEn = NAND WEn
DATA IN
EBI_AD[7:0] = NAND IO
WRHOLD
(0, 1, 2, ...)
EBI_AD[x] = NAND ALE
t
DS
t
DH
t
CS
t
CH
t
CLS
t
ALS
t
CLH
t
ALH
t
WP
t
WH
t
WC
The EBI_WRTIMING(n) setting requirements for satisfying the NAND Flash timing parameters for
command latching, address latching and data input timing are shown in Table 14.5 (p. 193) .
Table 14.5. EBI NAND Flash Write Timing
NAND Flash Write Timing Parameter EBI Write Timing Parameter Requirements
tADL <= t(WRHOLD) + t(WRSETUP) + t(WRSTRB)
tALS <= t(WRSETUP) + t(WRSTRB)
tCS <= t(WRSETUP) + t(WRSTRB)
tCLS <= t(WRSETUP) + t(WRSTRB)
tDS <= t(WRSETUP) + t(WRSTRB)
tALH <= t(WRHOLD)
tCH <= t(WRHOLD)
tCLH <= t(WRHOLD)
tDH <= t(WRHOLD)
tWC <= t(WRHOLD) + t(WRSETUP) + t(WRSTRB)
tWH <= t(WRHOLD) + t(WRSETUP)
tWP <= t(WRSTRB)
tWB (R/B edges can be detected by edge triggered GPIO
interrupts)
NAND Flash read timing is defined in the EBI_RDTIMING(n) register. Figure 14.30 (p. 194) shows
the NAND Flash data output timing assuming the D8A8 address mode.