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...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 183
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extension for the D16 mode is shown in Figure 14.9 (p. 180) and Figure 14.10 (p. 180) . A further
example for address extension in the multiplexed 16-bit data, 16-bit address mode of Section 14.3.2 (p.
178) is shown in Figure 14.16 (p. 183) . This is achieved by programming the MODE field in the
EBI_CTRL register to D16A16ALE and by enabling the required address lines via the ALB and APEN
bitfields of the EBI_ROUTE register.
Figure 14.16. EBI Extended Address Latch Setup
EBI
(EFM32)
External
Async.
Device
Latch
EBI_AD
ADDR LSBs
DATA
Control
ALE
ADDR MSBs
EBI_A
Read and write signals for using extended addressing in the D16A16ALE mode are shown in
Figure 14.17 (p. 183) and Figure 14.18 (p. 183) respectively for the case in which N extra address
lines have been enabled. At the start of the transaction the lower address bits are output on the EBI_AD
lines. The Latch is controlled by the ALE (Address Latch Enable) signal and stores the address. Then
the data is read or written according to operation. The higher address bits are output on the EBI_A lines
throughout the transfer.
Figure 14.17. EBI 16-bit Data Multiplexed Read Operation using Extended Addressing
ADDR[16:1]
EBI_AD[15:0]
EBI_ALE
ADDRSETUP
(1, 2, 3, ...)
Z DATA[15:0]
EBI_CSn
EBI_REn
Z
RDSETUP
(0, 1, 2, ...)
RDSTRB
(1, 2, 3, ...)
RDHOLD
(0, 1, 2, ...)
ADDR[16+ N:17]
EBI_A[16+ N-1:16]
Figure 14.18. EBI 16-bit Data Multiplexed Write Operation using Extended Addressing
ADDR[16:1]
EBI_AD[15:0]
EBI_ALE
ADDRSETUP
(1, 2, 3, ...)
DATA[15:0]
EBI_CSn
EBI_WEn
Z
WRSETUP
(0, 1, 2, ...)
WRSTRB
(1, 2, 3, ...)
WRHOLD
(0, 1, 2, ...)
ADDRHOLD
(0, 1, 2, ...)
ADDR[16+ N:17]
EBI_A[16+ N-1:16]
In order to minimize the pin requirements both the lower bound and the upper bound of the enabled
EBI_A lines can be set. This is done in the ALB and APEN bitfiels of the EBI_ROUTE register
respectively. For example, in case all memory banks use the 8-bit addressing mode D8A8, then the