User manual

...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 175
www.energymicro.com
14 EBI - External Bus Interface
0
1 2 3 4
EBI
(EFM32)
External
Async.
Device
Parallel Interface
Quick Facts
What?
The EBI is used for accessing external
parallel devices. The devices appear as a
part of the EFM32GG's internal memory map
and are therefore extremely simple to use.
Why?
Even though the EFM32GG is versatile, there
might be a need for specific external devices
such as extra RAM, FLASH, LCD, TFT. The
EBI simplifies the access to such devices.
How?
Through memory mapping the devices
appear as a part of the internal memory map.
When the processor performs read or writes
to the address range of the EBI, the EBI
handles the data transfers to and from the
external devices. The EBI may be interfaced
by the DMA, thus enabling operation in EM1.
14.1 Introduction
The External Bus Interface provides access to external parallel interface devices such as SRAM, FLASH,
ADCs and LCDs. The interface is memory mapped into the address bus of the Cortex-M3. This enables
seamless access from software without manually manipulating the IO settings each time a read or write
is performed. The data and address lines can be multiplexed in order to reduce the number of pins
required to interface the external devices. The bus timing is adjustable to meet specifications of the
external devices. The interface is limited to asynchronous devices and TFT.
14.2 Features
• Programmable interface for various memory types
• 4 memory bank regions
• Individual chip select line (EBI_CSn) per memory bank
• Accurate control of setup, strobe, hold and turn-around timing per memory bank
• Individual active high / active low setting of interface control signals per memory bank
• Slave read/write cycle extension per memory bank
• Page mode read
• NAND Flash support
• Both multiplexed and non-multiplexed address and data line configurations
• Up to 28 address lines
• Up to 16-bit data bus width
• Automatic translation when AHB transaction width and memory width differ
• Configurable prefetch from external device
• Write buffer to limit stalling of the Cortex-M3 or DMA
• TFT Direct Drive
• Programmable display and porch sizes