User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 163
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Bit Name Reset Access Description
31:1 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
0 CLEAR 0 W1 Watchdog Timer Clear
Clear watchdog timer. The bit must be written 4 watchdog cycles before the timeout.
Value Mode Description
0 UNCHANGED Watchdog timer is unchanged.
1 CLEARED Watchdog timer is cleared to 0.
12.5.3 WDOG_SYNCBUSY - Synchronization Busy Register
Offset Bit Position
0x008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
Access
R
R
Name
CMD
CTRL
Bit Name Reset Access Description
31:2 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
1 CMD 0 R WDOG_CMD Register Busy
Set when the value written to WDOG_CMD is being synchronized.
0 CTRL 0 R WDOG_CTRL Register Busy
Set when the value written to WDOG_CTRL is being synchronized.