User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 161
www.energymicro.com
12.4 Register Map
The offset register address is relative to the registers base address.
Offset Name Type Description
0x000 WDOG_CTRL RW Control Register
0x004 WDOG_CMD W1 Command Register
0x008 WDOG_SYNCBUSY R Synchronization Busy Register
12.5 Register Description
12.5.1 WDOG_CTRL - Control Register (Async Reg)
For more information about Asynchronous Registers please see Section 5.3 (p. 20) .
Offset Bit Position
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x0
0xF
0
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
CLKSEL
PERSEL
SWOSCBLOCK
EM4BLOCK
LOCK
EM3RUN
EM2RUN
DEBUGRUN
EN
Bit Name Reset Access Description
31:14 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
13:12 CLKSEL 0x0 RW Watchdog Clock Select
Selects the WDOG oscillator, ie. the clock on which the watchdog will run.
Value Mode Description
0 ULFRCO ULFRCO
1 LFRCO LFRCO
2 LFXO LFXO
11:8 PERSEL 0xF RW Watchdog Timeout Period Select.
Select watchdog timeout period.
Value Description
0 Timeout period of 9 watchdog clock cycles.
1 Timeout period of 17 watchdog clock cycles.
2 Timeout period of 33 watchdog clock cycles.
3 Timeout period of 65 watchdog clock cycles.
4 Timeout period of 129 watchdog clock cycles.
5 Timeout period of 257 watchdog clock cycles.
6 Timeout period of 513 watchdog clock cycles.
7 Timeout period of 1k watchdog clock cycles.
8 Timeout period of 2k watchdog clock cycles.
9 Timeout period of 4k watchdog clock cycles.
10 Timeout period of 8k watchdog clock cycles.
11 Timeout period of 16k watchdog clock cycles.
12 Timeout period of 32k watchdog clock cycles.
13 Timeout period of 64k watchdog clock cycles.
14 Timeout period of 128k watchdog clock cycles.
15 Timeout period of 256k watchdog clock cycles.