User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 152
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Bit Name Reset Access Description
Used to check the synchronization status of CMU_LFAPRESC0.
Value Description
0 CMU_LFAPRESC0 is ready for update
1 CMU_LFAPRESC0 is busy synchronizing new value
1 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
0 LFACLKEN0 0 R Low Frequency A Clock Enable 0 Busy
Used to check the synchronization status of CMU_LFACLKEN0.
Value Description
0 CMU_LFACLKEN0 is ready for update
1 CMU_LFACLKEN0 is busy synchronizing new value
11.5.20 CMU_FREEZE - Freeze Register
Offset Bit Position
0x054
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
Access
RW
Name
REGFREEZE
Bit Name Reset Access Description
31:1 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
0 REGFREEZE 0 RW Register Update Freeze
When set, the update of the Low Frequency clock control registers is postponed until this bit is cleared. Use this bit to update several
registers simultaneously.
Value Mode Description
0 UPDATE Each write access to a Low Frequency clock control register is updated into the Low
Frequency domain as soon as possible.
1 FREEZE The LE Clock Control registers are not updated with the new written value.
11.5.21 CMU_LFACLKEN0 - Low Frequency A Clock Enable Register 0
(Async Reg)
Offset Bit Position
0x058
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
Access
RW
RW
RW
RW
Name
LCD
LETIMER0
RTC
LESENSE
Bit Name Reset Access Description
31:4 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)