User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 149
www.energymicro.com
Bit Name Reset Access Description
0 HFRCORDY 0 W1 HFRCO Ready Interrupt Flag Clear
Write to 1 to clear the HFRCO Ready Interrupt Flag
11.5.16 CMU_IEN - Interrupt Enable Register
Offset Bit Position
0x03C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
RW
RW
Name
USBCHFCLKSEL
CALOF
CALRDY
AUXHFRCORDY
LFXORDY
LFRCORDY
HFXORDY
HFRCORDY
Bit Name Reset Access Description
31:8 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
7 USBCHFCLKSEL 0 RW USBC HFCLK Selected Interrupt Enable
Set to enable the USBC HFCLK Selected Interrupt.
6 CALOF 0 RW Calibration Overflow Interrupt Enable
Set to enable the Calibration Overflow Interrupt.
5 CALRDY 0 RW Calibration Ready Interrupt Enable
Set to enable the Calibration Ready Interrupt.
4 AUXHFRCORDY 0 RW AUXHFRCO Ready Interrupt Enable
Set to enable the AUXHFRCO Ready Interrupt.
3 LFXORDY 0 RW LFXO Ready Interrupt Enable
Set to enable the LFXO Ready Interrupt.
2 LFRCORDY 0 RW LFRCO Ready Interrupt Enable
Set to enable the LFRCO Ready Interrupt.
1 HFXORDY 0 RW HFXO Ready Interrupt Enable
Set to enable the HFXO Ready Interrupt.
0 HFRCORDY 0 RW HFRCO Ready Interrupt Enable
Set to enable the HFRCO Ready Interrupt.
11.5.17 CMU_HFCORECLKEN0 - High Frequency Core Clock Enable
Register 0
Offset Bit Position
0x040
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
Access
RW
RW
RW
RW
RW
RW
Name
EBI
LE
USB
USBC
AES
DMA