User manual

...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 140
www.energymicro.com
11.5.3 CMU_HFPERCLKDIV - High Frequency Peripheral Clock Division
Register
Offset Bit Position
0x008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1 0
Reset
1
0x0
Access
RW RW
Name
HFPERCLKEN
HFPERCLKDIV
Bit Name Reset Access Description
31:9 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
8 HFPERCLKEN 1 RW HFPERCLK Enable
Set to enable the HFPERCLK.
7:4 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
3:0 HFPERCLKDIV 0x0 RW HFPERCLK Divider
Specifies the clock divider for the HFPERCLK.
Value Mode Description
0 HFCLK HFPERCLK = HFCLK
1 HFCLK2 HFPERCLK = HFCLK/2
2 HFCLK4 HFPERCLK = HFCLK/4
3 HFCLK8 HFPERCLK = HFCLK/8
4 HFCLK16 HFPERCLK = HFCLK/16
5 HFCLK32 HFPERCLK = HFCLK/32
6 HFCLK64 HFPERCLK = HFCLK/64
7 HFCLK128 HFPERCLK = HFCLK/128
8 HFCLK256 HFPERCLK = HFCLK/256
9 HFCLK512 HFPERCLK = HFCLK/512
11.5.4 CMU_HFRCOCTRL - HFRCO Control Register
Offset Bit Position
0x00C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1 0
Reset
0x00
0x3
0x80
Access
RW RW RW
Name
SUDELAY
BAND
TUNING
Bit Name Reset Access Description
31:17 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
16:12 SUDELAY 0x00 RW HFRCO Start-up Delay
Always write this field to 0.
11 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)