User manual
...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 139
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Bit Name Reset Access Description
Set this to configure the external source for the HFXO. The oscillator setting takes effect when 1 is written to HFXOEN in
CMU_OSCENCMD. The oscillator setting is reset to default when 1 is written to HFXODIS in CMU_OSCENCMD.
Value Mode Description
0 XTAL 4-32 MHz crystal oscillator
1 BUFEXTCLK An AC coupled buffer is coupled in series with HFXTAL_N, suitable for external sine
wave (4-32 MHz). The sine wave should have a minimum of 200mV peak to peak.
2 DIGEXTCLK Digital external clock on HFXTAL_N pin. Oscillator is effectively bypassed.
11.5.2 CMU_HFCORECLKDIV - High Frequency Core Clock Division
Register
Offset Bit Position
0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0x0
Access
RW
RW
Name
HFCORECLKLEDIV
HFCORECLKDIV
Bit Name Reset Access Description
31:9 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
8 HFCORECLKLEDIV 0 RW Additional Division Factor For HFCORECLKLEDIV2
Additional division factor for HFCORECLKLE. When running at frequencies higher than 32 MHz, this must be set to DIV4
Value Mode Description
0 DIV2 Valid for frequencies 32 MHz and lower
1 DIV4 Must be used when HFCORECLK may go above 32 MHz
7:4 Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
3:0 HFCORECLKDIV 0x0 RW HFCORECLK Divider
Specifies the clock divider for HFCORECLK.
Value Mode Description
0 HFCLK HFCORECLK = HFCLK
1 HFCLK2 HFCORECLK = HFCLK/2
2 HFCLK4 HFCORECLK = HFCLK/4
3 HFCLK8 HFCORECLK = HFCLK/8
4 HFCLK16 HFCORECLK = HFCLK/16
5 HFCLK32 HFCORECLK = HFCLK/32
6 HFCLK64 HFCORECLK = HFCLK/64
7 HFCLK128 HFCORECLK = HFCLK/128
8 HFCLK256 HFCORECLK = HFCLK/256
9 HFCLK512 HFCORECLK = HFCLK/512