User manual

...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 12
www.energymicro.com
• Simplified stack-based programmer's model is compatible with traditional ARM architecture and
retains the programming simplicity of legacy 8- and 16-bit architectures
• Unaligned data storage and access
• Continuous storage of data requiring different byte lengths
• Data access in a single core access cycle
• Integrated power modes
• Sleep Now mode for immediate transfer to low power state
• Sleep on Exit mode for entry into low power state after the servicing of an interrupt
• Ability to extend power savings to other system components
• Optimized for low latency, nested interrupts
4.3 Functional Description
For a full functional description of the ARM Cortex-M3 (r2p1) implementation in the EFM32GG family,
the reader is referred to the EFM32 Cortex-M3 Reference Manual.
4.3.1 Interrupt Operation
Figure 4.1. Interrupt Operation
Module Cortex-M3 NVIC
IEN[n]
IF[n]
set clear
IFS[n] IFC[n]
Interrupt
condition
IRQ
SETENA[n]/CLRENA[n]
Interrupt
request
SETPEND[n]/CLRPEND[n]
set clear
Active interrupt
Software generated interrupt
The EFM32GG devices have up to 31 interrupt request lines (IRQ) which are connected to the Cortex-
M3. Each of these lines (shown in Table 4.1 (p. 13) ) is connected to one or more interrupt flags
in one or more modules. The interrupt flags are set by hardware on an interrupt condition. It is also
possible to set/clear the interrupt flags through the IFS/IFC registers. Each interrupt flag is then qualified
with its own interrupt enable bit (IEN register), before being OR'ed with the other interrupt flags to
generate the IRQ. A high IRQ line will set the corresponding pending bit (can also be set/cleared with
the SETPEND/CLRPEND bits in ISPR0/ICPR0) in the Cortex-M3 NVIC. The pending bit is then qualified
with a an enable bit (set/cleared with SETENA/CLRENA bits in ISER0/ICER0) before generating an
interrupt request to the core. Figure 4.1 (p. 12) illustrates the interrupt system. For more information
on how the interrupts are handled inside the Cortex-M3, the reader is referred to the EFM32 Cortex-
M3 Reference Manual.