User manual

...the world's most energy friendly microcontrollers
2012-04-24 - Giant Gecko Family - d0053_Rev0.96 110
www.energymicro.com
• MCU clock tree is inactive
• High frequency peripheral clock trees are active
• All peripheral functionality is available
10.3.1.3 EM2
• The high frequency oscillator is inactive
• The high frequency peripheral and MCU clock trees are inactive
• The low frequency oscillator and clock trees are active
• Low frequency peripheral functionality (RTC, Watchdog, LCD, LEUART, I
2
C, LETIMER, PCNT,
LESENSE, BURTC) is available
• Wakeup through peripheral interrupt or asynchronous pin interrupt
• RAM and register values are preserved
• DAC and OPAMPs are available
10.3.1.4 EM3
• Both high and low frequency oscillators and clock trees are inactive
• Wakeup through asynchronous pin interrupts, I
2
C address recognition or ACMP edge interrupt
• Watchdog, LETIMER and LESENSE enabled when ULFRCO (1 kHz clock) has been selected
• BURTC is available.
• All other peripheral functionality is disabled
• RAM and register values are preserved
• DAC and OPAMPs are available
10.3.1.5 EM4
• All oscillators and regulators are inactive, if Backup RTC is not enabled.
• RAM and register values are not preserved, except for the ones located in the Backup RTC.
• Optional GPIO state retention
• Wakeup from Backup RTC interrupt, external pin reset or pins that support EM4 wakeup
10.3.2 Entering a Low Energy Mode
A low energy mode is entered by first configuring the desired Energy Mode through the EMU_CTRL
register and the SLEEPDEEP bit in the Cortex-M3 System Control Register, see Table 10.2 (p. 111) .
A Wait For Interrupt (WFI) or Wait For Event (WFE) instruction from the Cortex-M3 triggers the transition
into a low energy mode.
The transition into a low energy mode can optionally be delayed until the lowest priority Interrupt Service
Routine (ISR) is exited, if the SLEEPONEXIT bit in the Cortex-M3 System Control Register is set.
Entering the lowest energy mode, EM4, is done by writing a sequence to the EM4CTRL bitfield in
the EMU_CTRL register. Writing a zero to the EM4CTRL bitfield will restart the power sequence.
EM2BLOCK prevents the EMU to enter EM2 or lower, and it will instead enter EM1.
EM3 is equal to EM2, except that the LFACLK/LFBCLK are disabled in EM3. The LFACLK/LFBCLK
must be disabled by the user before entering low energy mode.
The EMVREG bit in EMU_CTRL can be used to prevent the voltage regulator from being turned off in
low energy modes. The device will then essentially stay in EM1 when entering a low energy mode.