Specifications

C8051F330/1
92 Rev. 1.1
10.1. Power-On Reset
During power-up, the device is held in a reset state and the /RST pin is driven low until VDD settles above V
RST
. A
delay occurs before the device is released from reset; the delay decreases as the VDD ramp time increases (VDD
ramp time is defined as how fast VDD ramps from 0
V to V
RST
). Figure 10.2. plots the power-on and VDD monitor
reset timing. The maximum VDD ramp time is 1 ms; slower ramp times may cause the device to be released from
reset before VDD reaches the V
RST
level. For ramp times less than 1 ms, the power-on reset delay (T
PORDelay
) is typ-
ically less than 0.3 ms.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is set, all of
the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other resets). Since all resets
cause program execution to begin at the same location (0x0000) software can read the PORSF flag to determine if a
power-up was the cause of reset. The content of internal data memory should be assumed to be undefined after a
power-on reset. The VDD monitor is enabled following a power-on reset.
Power-On
Reset
VDD
Monitor
Reset
/RST
t
volts
1.0
2.0
Logic HIGH
Logic LOW
T
PORDelay
V
D
D
2.70
2.55
V
RST
VDD
Figure 10.2. Power-On and VDD Monitor Reset Timing