Specifications

C8051F330/1
Rev. 1.1 61
Comparator falling-edge occurrence, and the CP0RIF flag is set to logic 1 upon the Comparator rising-edge occur-
rence. Once set, these bits remain set until cleared by software. The Comparator rising-edge interrupt mask is enabled
by setting CP0RIE to a logic
1. The Comparator0 falling-edge interrupt mask is enabled by setting CP0FIE to a
logic
1.
The output state of the Comparator can be obtained at any time by reading the CP0OUT bit. The Comparator is
enabled by setting the CP0EN bit to logic
1, and is disabled by clearing this bit to logic 0.
Note that false rising edges and falling edges can be detected when the comparator is first powered on or if changes
are made to the hysteresis or response time control bits. Therefore, it is recommended that the rising-edge and falling-
edge flags be explicitly cleared to logic
0 a short time after the comparator is enabled or its mode bits have been
changed. This Power Up Time is specified in
Table 8.1 on page 65.