Specifications
C8051F330/1
60 Rev. 1.1
The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin. When
routed to a Port pin, the Comparator output is available asynchronous or synchronous to the system clock; the asyn
-
chronous output is available even in STOP mode (with no system clock active). When disabled, the Comparator out-
put (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state, and its supply current falls to less
than 100
nA. See Section “14.1. Priority Crossbar Decoder” on page 115 for details on configuring Comparator
outputs via the digital Crossbar. Comparator inputs can be externally driven from -0.25 V to (VDD) + 0.25 V without
damage or upset. The complete Comparator electrical specifications are given in
Table 8.1.
The Comparator response time may be configured in software via the CPT0MD register (see Figure 8.5). Selecting a
longer response time reduces the Comparator supply current. See Table 8.1 for complete timing and power consump-
tion specifications.
The Comparator hysteresis is software-programmable via its Comparator Control register CPT0CN. The user can
program both the amount of hysteresis voltage (referred to the input voltage) and the positive and negative-going
symmetry of this hysteresis around the threshold voltage.
The Comparator hysteresis is programmed using Bits3-0 in the Comparator Control Register CPT0CN (shown in
Figure 8.3). The amount of negative hysteresis voltage is determined by the settings of the CP0HYN bits. As shown
in Figure 8.2, settings of 20, 10 or 5 mV of negative hysteresis can be programmed, or negative hysteresis can be dis-
abled. In a similar way, the amount of positive hysteresis is determined by the setting the CP0HYP bits.
Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Interrupt enable
and priority control, see
Section “8.3. Interrupt Handler” on page 58). The CP0FIF flag is set to logic 1 upon a
Positive Hysteresis Voltage
(Programmed with CP0HYP Bits)
Negative Hysteresis Voltage
(Programmed by CP0HYN Bits)
VIN-
VIN+
INPUTS
CIRCUIT CONFIGURATION
+
_
CP0+
CP0-
CP0
VIN+
VIN-
OUT
V
OH
Positive Hysteresis
Disabled
Maximum
Positive Hysteresis
Negative Hysteresis
Disabled
Maximum
Negative Hysteresis
OUTPUT
V
OL
Figure 8.2. Comparator Hysteresis Plot