Specifications

C8051F330/1
Rev. 1.1 59
8. COMPARATOR0
C8051F330/1 devices include an on-chip programmable voltage comparator, Comparator0, shown in Figure 8.1.
The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two outputs that
are optionally available at the Port pins: a synchronous “latched” output (CP0), or an asynchronous “raw” output
(CP0A). The asynchronous CP0A signal is available even when in when the system clock is not active. This allows
the Comparator to operate and generate an output with the device in STOP mode. When assigned to a Port pin, the
Comparator output may be configured as open drain or push-pull (see
Section “14.2. Port I/O Initialization” on
page 117). Comparator0 may also be used as a reset source (see Section “10.5. Comparator0 Reset” on page 94).
The Comparator0 inputs are selected in the CPT0MX register (Figure 8.4). The CMX0P1-CMX0P0 bits select the
Comparator0 positive input; the CMX0N1-CMX0N0 bits select the Comparator0 negative input. Important Note
About Comparator Inputs: The Port pins selected as comparator inputs should be configured as analog inputs in
their associated Port configuration register, and configured to be skipped by the Crossbar (for details on Port configu
-
ration, see Section “14.3. General Purpose Port I/O” on page 120).
Figure 8.1. Comparator0 Functional Block Diagram
VDD
CPT0CN
Reset
Decision
Tree
+
-
Crossbar
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
(SYNCHRONIZER)
GND
CP0 +
P0.0
P0.2
P0.4
P0.6
CP0 -
P0.1
P0.3
P0.5
P0.7
CP0EN
CP0OUT
CP0RIF
CP0FIF
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
CPT0MX
CMX0N3
CMX0N2
CMX0N1
CMX0N0
CMX0P3
CMX0P2
CMX0P1
CMX0P0
CPT0MD
CP0RIE
CP0FIE
CP0MD1
CP0MD0
CP0
CP0A
P1.0
P1.2
P1.4
P1.6
P1.1
P1.3
P1.5
P1.7
CP0
Interrupt
0
1
0
1
CP0RIF
CP0FIF
0
1
CP0EN
0
1
EA