Specifications

C8051F330/1
Rev. 1.1 53
Figure 6.3. IDA0CN: IDA0 Control Register
Bit 7: IDA0EN: IDA0 Enable.
0: IDA0 Disabled.
1: IDA0 Enabled.
Bits 6-4: IDA0CM[2:0]: IDA0 Update Source Select bits.
000: DAC output updates on Timer 0 overflow.
001: DAC output updates on Timer 1 overflow.
010: DAC output updates on Timer 2 overflow.
011: DAC output updates on Timer 3 overflow.
100: DAC output updates on rising edge of CNVSTR.
101: DAC output updates on falling edge of CNVSTR.
110: DAC output updates on any edge of CNVSTR.
111: DAC output updates on write to IDA0H.
Bits 3-2: Unused. Read = 00b. Write = don’t care.
Bits 1:0: IDA0OMD[1:0]: IDA0 Output Mode Select bits.
00: 0.5 mA full-scale output current.
01: 1.0 mA full-scale output current.
1x: 2.0 mA full-scale output current.
R/W R/W R/W R/W R R R/W R/W Reset Value
IDA0EN IDA0CM - - IDA0OMD 01110010
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xB9
Figure 6.4. IDA0H: IDA0 Data Word MSB Register
Bits 7-0: IDA0 Data Word High-Order Bits.
Bits 7-0 are the most-significant bits of the 10-bit IDA0 Data Word.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0x97