Specifications

C8051F330/1
Rev. 1.1 51
6. 10-BIT CURRENT MODE DAC (IDA0, C8051F330 ONLY)
The C8051F330 device includes a 10-bit current-mode Digital-to-Analog Converter (IDAC). The maximum current
output of the IDAC can be adjusted for three different current settings; 0.5 mA, 1 mA, and 2 mA. The IDAC is
enabled or disabled with the IDA0EN bit in the IDA0 Control Register (see
Figure 6.3). When IDA0EN is set to ‘0’,
the IDAC port pin (P0.1) behaves as a normal GPIO pin. When IDA0EN is set to ‘1’, the digital output drivers and
weak pull-up for the IDAC pin are automatically disabled, and the pin is connected to the IDAC output. An internal
bandgap bias generator is used to generate a reference current for the IDAC whenever it is enabled. When using the
IDAC, bit 1 in the P0SKIP register should be set to ‘1’, to force the Crossbar to skip the IDAC pin.
6.1. IDA0 Output Scheduling
IDA0 features a flexible output update mechanism which allows for seamless full-scale changes and supports jitter-
free updates for waveform generation. Three update modes are provided, allowing IDAC output updates on a write to
IDA0H, on a Timer overflow, or on an external pin edge.
6.1.1. Update Output On-Demand
In its default mode (IDA0CN.[6:4] = ‘111’) the IDA0 output is updated “on-demand” on a write to the high-byte of
the IDA0 data register (IDA0H). It is important to note that writes to IDA0L are held in this mode, and have no effect
on the IDA0 output until a write to IDA0H takes place. If writing a full 10-bit word to the IDAC data registers, the
10-bit data word is written to the low byte (IDA0L) and high byte (IDA0H) data registers. Data is latched into IDA0
after a write to the IDA0H register, so the write sequence should be IDA0L followed by IDA0H if the full 10-bit
resolution is required. The IDAC can be used in 8-bit mode by initializing IDA0L to the desired value (typically
0x00), and writing data to only IDA0H (see
Section 6.2 for information on the format of the 10-bit IDAC data word
within the 16-bit SFR space).
IDA0
10
IDA0
IDA0CN
IDA0EN
IDA0CM2
IDA0CM1
IDA0CM0
IDA0OMD1
IDA0OMD0
IDA0HIDA0L
Latch
8
2
IDA0H
Timer 0 Timer 1 Timer 2 Timer 3
CNVSTR
Figure 6.1. IDA0 Functional Block Diagram