Specifications

C8051F330/1
36 Rev. 1.1
5.1. Analog Multiplexer
AMUX0 selects the positive and negative inputs to the ADC. Any of the following may be selected as the positive
input: Ports0-1, the on-chip temperature sensor, or the positive power supply (VDD). Any of the following may be
selected as the negative input: Ports0-1, VREF, or GND. When GND is selected as the negative input, ADC0 oper
-
ates in Single-ended Mode; all other times, ADC0 operates in Differential Mode. The ADC0 input channels are
selected in the AMX0P and AMX0N registers as described in
Figure 5.5 and Figure 5.6.
The conversion code format differs between Single-ended and Differential modes. The registers ADC0H and ADC0L
contain the high and low bytes of the output conversion code from the ADC at the completion of each conversion.
Data can be right-justified or left-justified, depending on the setting of the AD0LJST. When in Single-ended Mode,
conversion codes are represented as 10-bit unsigned integers. Inputs are measured from ‘0’ to VREF * 1023/1024.
Example codes are shown below for both right-justified and left-justified data. Unused bits in the ADC0H and
ADC0L registers are set to ‘0’.
When in Differential Mode, conversion codes are represented as 10-bit signed 2’s complement numbers. Inputs are
measured from -VREF to VREF * 511/512. Example codes are shown below for both right-justified and left-justified
data. For right-justified data, the unused MSBs of ADC0H are a sign-extension of the data word. For left-justified
data, the unused LSBs in the ADC0L register are set to ‘0’.
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be configured as
analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for analog input, set to ‘0’ the
corresponding bit in register PnMDIN (for n = 0,1). To force the Crossbar to skip a Port pin, set to ‘1’ the correspond
-
ing bit in register PnSKIP (for n = 0,1). See Section “14. Port Input/Output” on page 113 for more Port I/O config-
uration details.
Input Voltage Right-Justified ADC0H:ADC0L
(AD0LJST = 0)
Left-Justified ADC0H:ADC0L
(AD0LJST = 1)
VREF * 1023/1024 0x03FF 0xFFC0
VREF * 512/1024 0x0200 0x8000
VREF * 256/1024 0x0100 0x4000
0 0x0000 0x0000
Input Voltage Right-Justified ADC0H:ADC0L
(AD0LJST = 0)
Left-Justified ADC0H:ADC0L
(AD0LJST = 1)
VREF * 511/512 0x01FF 0x7FC0
VREF * 256/512 0x0100 0x4000
0 0x0000 0x0000
-VREF * 256/512 0xFF00 0xC000
- VREF 0xFC00 0x8000