Specifications

C8051F330/1
Rev. 1.1 35
5. 10-BIT ADC (ADC0, C8051F330 ONLY)
The ADC0 subsystem for the C8051F330 consists of two analog multiplexers (referred to collectively as AMUX0)
with 16 total input selections, and a 200
ksps, 10-bit successive-approximation-register ADC with integrated track-
and-hold and programmable window detector. The AMUX0, data conversion modes, and window detector are all
configurable under software control via the Special Function Registers shown in
Figure 5.1. ADC0 operates in both
Single-ended and Differential modes, and may be configured to measure Ports0-1, the Temperature Sensor output, or
VDD with respect to Ports0-1 or GND. The ADC0 subsystem is enabled only when the AD0EN bit in the ADC0
Control register (ADC0CN) is set to logic
1. The ADC0 subsystem is in low power shutdown when this bit is logic 0.
ADC0CF
AD0LJST
AD0SC0 AD0SC1 AD0SC2 AD0SC3 AD0SC4
10-Bit
SAR
ADC
REF
SYSCLK
ADC0H
32
ADC0CN
AD0CM0 AD0CM1 AD0CM2
AD0WINT
AD0BUSY
AD0INT
AD0TM
AD0EN
Timer 0 Overflow
Timer 2 Overflow
Timer 1 Overflow
Start
Conversion
000 AD0BUSY (W)
VDD
ADC0LTH
18-to-1
AMUX
AD0WINT
Temp
Sensor
18-to-1
AMUX
VDD
P0.0
P0.7
001
010
011
100
CNVSTR Input
Window
Compare
Logic
P1.0
P1.7
GND
P0.0
P0.7
P1.0
P1.7
101 Timer 3 Overflow
ADC0LTL
ADC0GTH ADC0GTL
ADC0L
AMX0P
AMX0P4 AMX0P3 AMX0P2 AMX0P1 AMX0P0
AMX0N
AMX0N4 AMX0N3 AMX0N2 AMX0N1 AMX0N0
(+)
(-)
VREF
Figure 5.1. ADC0 Functional Block Diagram