Specifications

C8051F330/1
28 Rev. 1.1
4. PINOUT AND PACKAGE DEFINITIONS
Table 4.1. Pin Definitions for the C8051F330/1
Name
Pin
Numbers
Type Description
VDD 3 Power Supply Voltage.
GND 2 Ground.
/RST/
C2CK
4 D I/O
D I/O
Device Reset. Open-drain output of internal POR or VDD moni-
tor. An external source can initiate a system reset by driving this
pin low for at least 10
µs.
Clock signal for the C2 Debug Interface.
P2.0/
C2D
5 D I/O
D I/O
Port 3.0. See Section 14 for a complete description.
Bi-directional data signal for the C2 Debug Interface.
P0.0/
VREF
1 D I/O or
A In
A In
Port 0.0. See Section 14 for a complete description.
External VREF input. See Section 7 for a complete description.
P0.1
IDA0
20 D I/O or
A In
AOut
Port 0.1. See Section 14 for a complete description.
IDA0 Output. See Section 6 for a complete description.
P0.2/
XTAL1
19 D I/O or
A In
A In
Port 0.2. See Section 14 for a complete description.
External Clock Input. This pin is the external oscillator return for
a crystal or resonator. See
Section 13 for a complete description.
P0.3/
XTAL2
18 D I/O or
A In
A I/O or
D In
Port 0.3. See Section 14 for a complete description.
External Clock Output. For an external crystal or resonator, this
pin is the excitation driver. This pin is the external clock input for
CMOS, capacitor, or RC oscillator configurations. See
Section 13
for a complete description.
P0.4 17 D I/O or
A In
Port 0.4. See Section 14 for a complete description.
P0.5 16 D I/O or
A In
Port 0.5. See Section 14 for a complete description.