Specifications

C8051F330/1
192 Rev. 1.1
19.2.5. 8-Bit Pulse Width Modulator Mode
Each module can be used independently to generate a pulse width modulated (PWM) output on its associated CEXn
pin. The frequency of the output is dependent on the timebase for the PCA counter/timer. The duty cycle of the PWM
output signal is varied using the module's PCA0CPLn capture/compare register. When the value in the low byte of the
PCA counter/timer (PCA0L) is equal to the value in PCA0CPLn, the output on the CEXn pin will be set. When the
count value in PCA0L overflows, the CEXn output will be reset (see
Figure 19.8). Also, when the counter/timer low
byte (PCA0L) overflows from 0xFF to 0x00, PCA0CPLn is reloaded automatically with the value stored in the mod-
ule’s capture/compare high byte (PCA0CPHn) without software intervention. Setting the ECOMn and PWMn bits in
the PCA0CPMn register enables 8-Bit Pulse Width Modulator mode. The duty cycle for 8-Bit PWM Mode is given
by
Equation 19.2.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/Compare
registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit to ‘0’; writing to
PCA0CPHn sets ECOMn to ‘1’.
Using Equation 19.2, the largest duty cycle is 100% (PCA0CPHn = 0), and the smallest duty cycle is 0.39%
(PCA0CPHn = 0xFF). A 0% duty cycle may be generated by clearing the ECOMn bit to ‘0’.
DutyCycle
256 PCA0CPHn–()
256
---------------------------------------------------=
Equation 19.2. 8-Bit PWM Duty Cycle
8-bit
Comparator
PCA0L
PCA0CPLn
PCA0CPHn
CEXn
Crossbar Port I/O
Enable
Overflow
PCA Timebase
00x0 x
Q
Q
SET
CLR
S
R
match
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
0
ENB
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset
Figure 19.8. PCA 8-Bit PWM Mode Diagram