Specifications

C8051F330/1
Rev. 1.1 19
1.2. On-Chip Memory
The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with the
upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and direct
addressing accesses the 128 byte SFR address space. The lower 128 bytes of RAM are accessible via direct and indi
-
rect addressing. The first 32 bytes are addressable as four banks of general purpose registers, and the next 16 bytes
can be byte addressable or bit addressable.
Program memory consists of 8k bytes of FLASH. This memory may be reprogrammed in-system in 512 byte sectors,
and requires no special off-chip programming voltage. See
Figure 1.5 for the MCU system memory map.
PROGRAM/DATA MEMORY
(FLASH)
(Direct and Indirect
Addressing)
0x00
0x7F
Upper 128 RAM
(Indirect Addressing
Only)
0x80
0xFF
Special Function
Register's
(Direct Addressing Only)
DATA MEMORY (RAM)
General Purpose
Registers
0x1F
0x20
0x2F
Bit Addressable
Lower 128 RAM
(Direct and Indirect
Addressing)
0x30
INTERNAL DATA ADDRESS SPACE
EXTERNAL DATA ADDRESS SPACE
XRAM - 512 Bytes
(accessable using MOVX
instruction)
0x0000
0x01FF
Same 512 bytes as from
0x0000 to 0x01FF, wrapped
on 512-byte boundaries
0x0200
0xFFFF
8K FLASH
(In-System
Programmable in 512
Byte Sectors)
0x0000
RESERVED
0x1E00
0x1DFF
0x1FFF
Figure 1.5. On-Board Memory Map