Specifications

C8051F330/1
182 Rev. 1.1
18.3.2. 8-bit Timers with Auto-Reload
When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TH3 and TL3). Both 8-bit timers operate in auto-reload
mode as shown in
Figure 18.12. TMR3RLL holds the reload value for TL3; TMR3RLH holds the reload value for
TH3. The TR3 bit in TMR3CN handles the run control for TH3. TL3 is always running when configured for 8-bit
Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock source
divided by 8. The Timer 3 Clock Select bits (T3MH and T3ML in CKCON) select either SYSCLK or the clock
defined by the Timer 3 External Clock Select bit (T3XCLK in TMR3CN), as follows:
The TF3H bit is set when TH3 overflows from 0xFF to 0x00; the TF3L bit is set when TL3 overflows from 0xFF to
0x00. When Timer 3 interrupts are enabled (IE.5), an interrupt is generated each time TH3 overflows. If Timer 3
interrupts are enabled and TF3LEN (TMR3CN.5) is set, an interrupt is generated each time either TL3 or TH3 over
-
flows. When TF3LEN is enabled, software must check the TF3H and TF3L flags to determine the source of the
Timer 3 interrupt. The TF3H and TF3L interrupt flags are not cleared by hardware and must be manually cleared by
software
.
T3MH T3XCLK TH3 Clock Source T3ML T3XCLK TL3 Clock Source
0 0 SYSCLK / 12 0 0 SYSCLK / 12
0 1 External Clock / 8 0 1 External Clock / 8
1 X SYSCLK 1 X SYSCLK
Figure 18.19. Timer 3 8-Bit Mode Block Diagram
SYSCLK
TCLK
0
1
TR3
External Clock / 8
SYSCLK / 12
0
1
T3XCLK
1
0
TH3
TMR3RLH
Reload
Reload
TCLK
TL3
TMR3RLL
Interrupt
TMR3CN
T3SPLIT
TF3CEN
TF3LEN
TF3L
TF3H
T3XCLK
TR3
To ADC
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M