Specifications

C8051F330/1
Rev. 1.1 181
18.3. Timer 3
Timer 3 is a 16-bit timer formed by two 8-bit SFRs: TMR3L (low byte) and TMR3H (high byte). Timer 3 may oper-
ate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T3SPLIT bit (TMR3CN.3) defines the Timer 3
operation mode.
Timer 3 may be clocked by the system clock, the system clock divided by 12, or the external oscillator source divided
by 8. The external clock mode is ideal for real-time clock (RTC) functionality, where the internal oscillator drives the
system clock while Timer 3 (and/or the PCA) is clocked by an external precision oscillator. Note that the external
oscillator source divided by 8 is synchronized with the system clock.
18.3.1. 16-bit Timer with Auto-Reload
When T3SPLIT (TMR3CN.3) is zero, Timer 3 operates as a 16-bit timer with auto-reload. Timer 3 can be clocked by
SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. As the 16-bit timer register
increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 3 reload registers (TMR3RLH and
TM32RLL) is loaded into the Timer 3 register as shown in
Figure 18.11, and the Timer 3 High Byte Overflow Flag
(TMR3CN.7) is set. If Timer 3 interrupts are enabled (if IE.5 is set), an interrupt will be generated on each Timer 3
overflow. Additionally, if Timer 3 interrupts are enabled and the TF3LEN bit is set (TMR3CN.5), an interrupt will be
generated each time the lower 8 bits (TL3) overflow from 0xFF to 0x00.
Figure 18.18. Timer 3 16-Bit Mode Block Diagram
External Clock / 8
SYSCLK / 12
SYSCLK
TL3 TH3
TMR3RLL TMR3RLH
Reload
TCLK
0
1
TR3
TMR3CN
T3SPLIT
TF3CEN
TF3L
TF3H
T3XCLK
TR3
0
1
T3XCLK
Interrupt
TF3LEN
To ADC
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M