Specifications

C8051F330/1
168 Rev. 1.1
Tabl e 17.1. SPI Slave Timing Parameters
PARAMETER DESCRIPTION MIN MAX UNITS
MASTER MODE TIMING
†
(See Figure 17.12 and Figure 17.13)
T
MCKH
SCK High Time 1*T
SYSCLK
ns
T
MCKL
SCK Low Time 1*T
SYSCLK
ns
T
MIS
MISO Valid to SCK Shift Edge 1*T
SYSCLK
+ 20 ns
T
MIH
SCK Shift Edge to MISO Change 0 ns
SLAVE MODE TIMING
†
(See Figure 17.14 and Figure 17.15)
T
SE
NSS Falling to First SCK Edge 2*T
SYSCLK
ns
T
SD
Last SCK Edge to NSS Rising 2*T
SYSCLK
ns
T
SEZ
NSS Falling to MISO Valid 4*T
SYSCLK
ns
T
SDZ
NSS Rising to MISO High-Z 4*T
SYSCLK
ns
T
CKH
SCK High Time 5*T
SYSCLK
ns
T
CKL
SCK Low Time 5*T
SYSCLK
ns
T
SIS
MOSI Valid to SCK Sample Edge 2*T
SYSCLK
ns
T
SIH
SCK Sample Edge to MOSI Change 2*T
SYSCLK
ns
T
SOH
SCK Shift Edge to MISO Change 4*T
SYSCLK
ns
T
SLH
Last SCK Edge to MISO Change (CKPHA = 1 ONLY) 6*T
SYSCLK
8*T
SYSCLK
ns
†
T
SYSCLK
is equal to one period of the device system clock (SYSCLK).