Specifications

C8051F330/1
Rev. 1.1 155
17. ENHANCED SERIAL PERIPHERAL INTERFACE (SPI0)
The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous serial bus.
SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves
on a single SPI bus. The slave-select (NSS) signal can be configured as an input to select SPI0 in slave mode, or to
disable Master Mode operation in a multi-master environment, avoiding contention on the SPI bus when more than
one master attempts simultaneous data transfers. NSS can also be configured as a chip-select output in master mode,
or disabled for 3-wire operation. Additional general purpose port I/O pins can be used to select multiple slave devices
in master mode.
Figure 17.1. SPI Block Diagram
SFR Bus
Data Path
Control
SFR Bus
Write
SPI0DAT
Receive Data Buffer
SPI0DAT
01234567
Shift Register
SPI CONTROL LOGIC
SPI0CKR
SCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCR1 SCR0
SPI0CFG SPI0CN
Pin Interface
Control
Pin
Control
Logic
C
R
O
S
S
B
A
R
Port I/O
Read
SPI0DAT
SPI IRQ
Tx Data
Rx Data
SCK
MOSI
MISO
NSS
Transmit Data Buffer
Clock Divide
Logic
SYSCLK
CKPHA
CKPOL SLVSEL NSSMD1 NSSMD0 SPIBSY MSTEN NSSIN SRMT RXBMT SPIF WCOL MODF RXOVRN TXBMT SPIEN