Specifications

C8051F330/1

148 Rev. 1.1

16.2.2. 9-Bit UART

9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programmable ninth

data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80 (SCON0.3), which

is assigned by user software. It can be assigned the value of the parity flag (bit P in register PSW) for error detection,

or used in multiprocessor communications. On receive, the ninth data bit goes into RB80 (SCON0.2) and the stop bit

is ignored.

Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit Interrupt

Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin

any time after the REN0 Receive Enable bit (SCON0.4) is set to ‘1’. After the stop bit is received, the data byte will

be loaded into the SBUF0 receive register if the following conditions are met: (1) RI0 must be logic

0, and (2) if

MCE0 is logic

1, the 9th bit must be logic 1 (when MCE0 is logic 0, the state of the ninth data bit is unimportant). If

these conditions are met, the eight bits of data are stored in SBUF0, the ninth bit is stored in RB80, and the RI0 flag is

set to ‘1’. If the above conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not be set to

‘1’. A UART0 interrupt will occur if enabled when either TI0 or RI0 is set to ‘1’.

Figure 16.5. 9-Bit UART Timing Diagram

D1D0 D2 D3 D4 D5 D6 D7

START

BIT

MARK

STOP

BIT

BIT TIMES

BIT SAMPLING

SPACE