Specifications

C8051F330/1
Rev. 1.1 139
15.5. SMBus Transfer Modes
The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be operating
in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or Slave Receiver. The
SMBus interface enters Master Mode any time a START is generated, and remains in Master Mode until it loses an
arbitration or generates a STOP. An SMBus interrupt is generated at the end of all SMBus byte frames; however, note
that the interrupt is generated before the ACK cycle when operating as a receiver, and after the ACK cycle when
operating as a transmitter.
15.5.1. Master Transmitter Mode
Serial data is transmitted on SDA while the serial clock is output on SCL. The SMBus interface generates the START
condition and transmits the first byte containing the address of the target slave and the data direction bit. In this case
the data direction bit (R/W) will be logic
0 (WRITE). The master then transmits one or more bytes of serial data.
After each byte is transmitted, an acknowledge bit is generated by the slave. The transfer is ended when the STO bit
is set and a STOP is generated. Note that the interface will switch to Master Receiver Mode if SMB0DAT is not writ
-
ten following a Master Transmitter interrupt. Figure 15.8 shows a typical Master Transmitter sequence. Two transmit
data bytes are shown, though any number of bytes may be transmitted. Notice that the ‘data byte transferred’ inter-
rupts occur after the ACK cycle in this mode.
A AAS W PData Byte Data ByteSLA
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
Received by SMBus
Interface
Transmitted by
SMBus Interface
Interrupt Interrupt InterruptInterrupt
Figure 15.8. Typical Master Transmitter Sequence