Specifications

C8051F330/1
Rev. 1.1 131
15.4. Using the SMBus
The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting control for serial
transfers; higher level protocol is determined by user software. The SMBus interface provides the following applica
-
tion-independent features:
• Byte-wise serial data transfers
• Clock signal generation on SCL (Master Mode only) and SDA data synchronization
• Timeout/bus error recognition, as defined by the SMB0CF configuration register
• START/STOP timing, detection, and generation
• Bus arbitration
• Interrupt generation
• Status information
SMBus interrupts are generated for each data byte or slave address that is transferred. When transmitting, this inter-
rupt is generated after the ACK cycle so that software may read the received ACK value; when receiving data, this
interrupt is generated before the ACK cycle so that software may define the outgoing ACK value. See
Section
“15.5. SMBus Transfer Modes” on page 139 for more details on transmission sequences.
Interrupts are also generated to indicate the beginning of a transfer when a master (START generated), or the end of a
transfer when a slave (STOP detected). Software should read the SMB0CN (SMBus Control register) to find the
cause of the SMBus interrupt. The SMB0CN register is described in
Section “15.4.2. SMB0CN Control Register”
on page 135; Table 15.4 provides a quick SMB0CN decoding reference.
SMBus configuration options include:
• Timeout detection (SCL Low Timeout and/or Bus Free Timeout)
• SDA setup and hold time extensions
• Slave event enable/disable
• Clock source selection
These options are selected in the SMB0CF register, as described in Section “15.4.1. SMBus Configuration Regis-
ter” on page 132.