Specifications

C8051F330/1
128 Rev. 1.1
15.1. Supporting Documents
It is assumed the reader is familiar with or has access to the following supporting documents:
1. The I
2
C-Bus and How to Use It (including specifications), Philips Semiconductor.
2. The I
2
C-Bus Specification -- Version 2.0, Philips Semiconductor.
3. System Management Bus Specification -- Version 1.1, SBS Implementers Forum.
15.2. SMBus Configuration
Figure 15.2 shows a typical SMBus configuration. The SMBus specification allows any recessive voltage between
3.0 V and 5.0 V; different devices on the bus may operate at different voltage levels. The bi-directional SCL (serial
clock) and SDA (serial data) lines must be connected to a positive power supply voltage through a pull-up resistor or
similar circuit. Every device connected to the bus must have an open-drain or open-collector output for both the SCL
and SDA lines, so that both are pulled high (recessive state) when the bus is free. The maximum number of devices
on the bus is limited only by the requirement that the rise and fall times on the bus not exceed 300
ns and 1000 ns,
respectively.
Figure 15.2. Typical SMBus Configuration
VDD = 5V
Master
Device
Slave
Device 1
Slave
Device 2
VDD = 3V VDD = 5V VDD = 3V
SDA
SCL