Specifications

C8051F330/1
Rev. 1.1 127
15. SMBUS
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Manage-
ment Bus Specification, version 1.1, and compatible with the I
2
C serial bus. Reads and writes to the interface by the
system controller are byte oriented with the SMBus interface autonomously controlling the serial transfer of the data.
Data can be transferred at up to 1/10th of the system clock as a master or slave (this can be faster than allowed by the
SMBus specification, depending on the system clock used). A method of extending the clock-low duration is avail
-
able to accommodate devices with different speed capabilities on the same bus.
The SMBus interface may operate as a master and/or slave, and may function on a bus with multiple masters. The
SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration logic,
and START/STOP control and generation. Three SFRs are associated with the SMBus: SMB0CF configures the
SMBus; SMB0CN controls the status of the SMBus; and SMB0DAT is the data register, used for both transmitting
and receiving SMBus data and slave addresses.
Figure 15.1. SMBus Block Diagram
Data Path
Control
SMBUS CONTROL LOGIC
C
R
O
S
S
B
A
R
SCL
FILTER
N
SDA
Control
SCL
Control
Arbitration
SCL Synchronization
IRQ Generation
SCL Generation (Master Mode)
SDA Control
Interrupt
Request
Port I/O
SMB0CN
S
T
A
A
C
K
R
Q
A
R
B
L
O
S
T
A
C
K
S
I
T
X
M
O
D
E
M
A
S
T
E
R
S
T
O
01
00
10
11
T0 Overflow
T1 Overflow
TMR2H Overflow
TMR2L Overflow
SMB0CF
E
N
S
M
B
I
N
H
B
U
S
Y
E
X
T
H
O
L
D
S
M
B
T
O
E
S
M
B
F
T
E
S
M
B
C
S
1
S
M
B
C
S
0
01234567
SMB0DAT
SDA
FILTER
N