Specifications

C8051F330/1
116 Rev. 1.1
Registers XBR0 and XBR1 are used to assign the digital I/O resources to the physical I/O Port pins. Note that when
the SMBus is selected, the Crossbar assigns both pins associated with the SMBus (SDA and SCL); when the UART is
selected, the Crossbar assigns both pins associated with the UART (TX and RX). UART0 pin assignments are fixed
for bootloading purposes: UART TX0 is always assigned to P0.4; UART RX0 is always assigned to P0.5. Standard
Port I/Os appear contiguously after the prioritized functions have been assigned.
Important Note: The SPI can be operated in either 3-wire or 4-wire modes, pending the state of the NSSMD1-
NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not be routed to a Port pin.
Figure 14.4. Crossbar Priority Decoder with Crystal Pins Skipped
P2
V
RE
F
IDA x1 x2 CNVSTR
01234567012345670
*NSS is only pinned out in 4-wire SPI Mode
SYSCLK
CEX0
CEX1
CEX2
ECI
0011000000000000
CP0A
Special Function Signals are not assigned by the crossbar.
When these signals are enabled, the CrossBar must be
manually configured to skip their corresponding port pins.
Port pin potentially available to peripheral
SF Signals
T1
P0SKIP[7:0]
T0
P1SKIP[7:0]
SF Signals
PIN I/O
TX0
CP0
SDA
SCL
P0 P1
NSS*
SCK
MISO
MOSI
RX0