Specifications

C8051F330/1
Rev. 1.1 113
14. PORT INPUT/OUTPUT
Digital and analog resources are available through 17 I/O pins. Port pins are organized as two byte-wide Ports and
one 1-bit Port. Each of the Port pins can be defined as general-purpose I/O (GPIO) or analog input; Port pins P0.0 -
P1.7 can be assigned to one of the internal digital resources as shown in
Figure 14.3. The designer has complete con-
trol over which functions are assigned, limited only by the number of physical I/O pins. This resource assignment
flexibility is achieved through the use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin can always
be read in the corresponding Port latch, regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder (Figure 14.3
and Figure 14.4). The registers XBR0 and XBR1, defined in Figure 14.5 and Figure 14.6, are used to select internal
digital functions.
All Port I/Os are 5 V tolerant (refer to Figure 14.2 for the Port cell circuit). The Port I/O cells are configured as either
push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1). Complete Electrical Specifi-
cations for Port I/O are given in Table 14.1 on page 126.
XBR0, XBR1,
PnSKIP Registers
Digital
Crossbar
Priority
Decoder
2
P0
I/O
Cells
P0.0
P0.7
8
PnMDOUT,
PnMDIN Registers
UART
(Internal Digital Signals)
Highest
Priority
Lowest
Priority
SYSCLK
2
SMBus
T0, T1
2
4
PCA
4
SPI
CP0
Outputs
2
P1
I/O
Cells
P1.0
P1.7
8
(Port Latches)
P0
(P0.0-P0.7)
(P1.0-P1.7)
8
8
P1
Figure 14.1. Port I/O Functional Block Diagram