Specifications

C8051F330/1
112 Rev. 1.1
erals (timers, PCA) when the internal oscillator is selected as the system clock. The system clock may be switched
on-the-fly between the internal and external oscillator, so long as the selected oscillator is enabled and has settled.
The internal oscillator requires little start-up time and may be selected as the system clock immediately following the
OSCICN write that enables the internal oscillator. External crystals and ceramic resonators typically require a start-up
time before they are settled and ready for use as the system clock. The Crystal Valid Flag (XTLVLD in register
OSCXCN) is set to ‘1’ by hardware when the external oscillator is settled. To avoid reading a false XTLVLD, in
crystal mode software should delay at least 1
ms between enabling the external oscillator and checking
XTLVLD. RC and C modes typically require no startup time.
Table 13.1. Internal Oscillator Electrical Characteristics
VDD = 2.7 to 3.6V; Ta = -40°C to +85°C unless otherwise specified
PARAMETER CONDITIONS MIN TYP MAX UNITS
Internal High-Frequency Oscillator (Using Factory-Calibrated Settings)
Oscillator Frequency IFCN = 11b 24 24.5 25 MHz
Oscillator Supply Current (from
VDD)
25°C, VDD = 3.0 V,
OSCICN.7 = 1
450 µA
Power Supply Sensitivity Constant Temperature 0.3 ± 0.1† % / V
Temperature Sensitivity Constant Supply 50 ± 10†
ppm / °C
Internal Low-Frequency Oscillator (Using Factory-Calibrated Settings)
Oscillator Frequency OSCLD = 11b 72 80 88 kHz
Oscillator Supply Current (from
VDD)
25°C, VDD = 3.0 V,
OSCLCN.7 = 1
5.5 µA
Power Supply Sensitivity Constant Temperature -3 ± 0.1† % / V
Temperature Sensitivity Constant Supply 20 ± 8†
ppm / °C
†Represents Mean ± 1 Standard Deviation
Figure 13.6. CLKSEL: Clock Select Register
Bits7-2: UNUSED. Read = 000000b, Write = don't care.
Bits1-0: SEL[1:0]: System Clock Source Select Bits.
00: SYSCLK derived from the Internal High-Frequency Oscillator and scaled per the IFCN bits in
register OSCICN.
01: SYSCLK derived from the External Oscillator circuit.
10: SYSCLK derived from the Internal Low-Frequency Oscillator and scaled per the OSCLD bits in
register OSCLCN.
11: reserved.
RRRRRRR/WR/WReset Value
- - - - - - SEL1 SEL0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xA9