Specifications

C8051F330/1
Rev. 1.1 11
Figure 18.8. TL1: Timer 1 Low Byte ....................................................................................176
Figure 18.9. TH0: Timer 0 High Byte ...................................................................................176
Figure 18.10. TH1: Timer 1 High Byte .................................................................................176
Figure 18.11. Timer 2 16-Bit Mode Block Diagram .............................................................177
Figure 18.12. Timer 2 8-Bit Mode Block Diagram ...............................................................178
Figure 18.13. TMR2CN: Timer 2 Control Register ..............................................................179
Figure 18.14. TMR2RLL: Timer 2 Reload Register Low Byte ............................................180
Figure 18.15. TMR2RLH: Timer 2 Reload Register High Byte ...........................................180
Figure 18.16. TMR2L: Timer 2 Low Byte ............................................................................180
Figure 18.17. TMR2H Timer 2 High Byte ............................................................................180
Figure 18.18. Timer 3 16-Bit Mode Block Diagram .............................................................181
Figure 18.19. Timer 3 8-Bit Mode Block Diagram ...............................................................182
Figure 18.20. TMR3CN: Timer 3 Control Register ..............................................................183
Figure 18.21. TMR3RLL: Timer 3 Reload Register Low Byte ............................................184
Figure 18.22. TMR3RLH: Timer 3 Reload Register High Byte ...........................................184
Figure 18.23. TMR3L: Timer 3 Low Byte ............................................................................184
Figure 18.24. TMR3H Timer 3 High Byte ............................................................................184
19. PROGRAMMABLE COUNTER ARRAY
Figure 19.1. PCA Block Diagram..........................................................................................185
Figure 19.2. PCA Counter/Timer Block Diagram.................................................................186
Table 19.1. PCA Timebase Input Options............................................................................186
Figure 19.3. PCA Interrupt Block Diagram...........................................................................187
Table 19.2. PCA0CPM Register Settings for PCA Capture/Compare Modules..................187
Figure 19.4. PCA Capture Mode Diagram ............................................................................188
Figure 19.5. PCA Software Timer Mode Diagram................................................................189
Figure 19.6. PCA High Speed Output Mode Diagram ..........................................................190
Figure 19.7. PCA Frequency Output Mode...........................................................................191
Figure 19.8. PCA 8-Bit PWM Mode Diagram ......................................................................192
Figure 19.9. PCA 16-Bit PWM Mode ...................................................................................193
Figure 19.10. PCA Module 2 with Watchdog Timer Enabled ..............................................194
Table 19.3. Watchdog Timer Timeout Intervals† ................................................................195
Figure 19.11. PCA0CN: PCA Control Register ....................................................................196
Figure 19.12. PCA0MD: PCA Mode Register ......................................................................197
Figure 19.13. PCA0CPMn: PCA Capture/Compare Mode Registers ...................................198
Figure 19.14. PCA0L: PCA Counter/Timer Low Byte .........................................................199
Figure 19.15. PCA0H: PCA Counter/Timer High Byte ........................................................199
Figure 19.16. PCA0CPLn: PCA Capture Module Low Byte ................................................200
Figure 19.17. PCA0CPHn: PCA Capture Module High Byte...............................................200
20. C2 INTERFACE
Figure 20.1. C2ADD: C2 Address Register ..........................................................................201
Figure 20.2. DEVICEID: C2 Device ID Register .................................................................201
Figure 20.3. REVID: C2 Revision ID Register .....................................................................202
Figure 20.4. FPCTL: C2 FLASH Programming Control Register ........................................202
Figure 20.5. FPDAT: C2 FLASH Programming Data Register ............................................202
Figure 20.6. Typical C2 Pin Sharing .....................................................................................203