Specifications

C8051F330/1
108 Rev. 1.1
13.2. Programmable Internal Low-Frequency (L-F) Oscillator
All C8051F330/1 devices include a programmable low-frequency internal oscillator, which is calibrated to a nominal
frequency of 80
kHz. The low-frequency oscillator circuit includes a divider that can be changed to divide the clock
by 1, 2, 4, or 8, using the OSCLD bits in the OSCLCN register (see
Figure 13.4). Additionally, the OSCLF bits
(OSCLCN5:2) can be used to adjust the oscillator’s output frequency.
13.2.1. Calibrating the Internal L-F Oscillator
Timers 2 and 3 include capture functions that can be used to capture the oscillator frequency, when running from a
known time base. When either Timer
2 or Timer 3 is configured for L-F Oscillator Capture Mode, a falling edge
(Timer
2) or rising edge (Timer 3) of the low-frequency oscillator’s output will cause a capture event on the corre-
sponding timer. As a capture event occurs, the current timer value (TMRnH:TMRnL) is copied into the timer reload
registers (TMRnRLH:TMRnRLL). By recording the difference between two successive timer capture values, the
low-frequency oscillator’s period can be calculated. The OSCLF bits can then be adjusted to produce the desired
oscillator period. The L-F oscillator’s period can be tuned in steps of approximately 3%. This is described by
Equation 13.2, where f
BASE
is the frequency of the L-F oscillator before changing the OSCLF bits, ∆T is the resulting
change in the L-F oscillator period, and ∆OSCLF is the change to the OSCLF bits.
Figure 13.4. OSCLCN: Internal L-F Oscillator Control Register
Bit7: OSCLEN: Internal L-F Oscillator Enable.
0: Internal L-F Oscillator Disabled.
1: Internal L-F Oscillator Enabled.
Bit6: OSCLRDY: Internal L-F Oscillator Ready.
0: Internal L-F Oscillator frequency not stabilized.
1: Internal L-F Oscillator frequency stabilized.
Bits5-2: OSCLF[3:0]: Internal L-F Oscillator Frequency Control bits.
Fine-tune control bits for the Internal L-F oscillator frequency. When set to 0000b, the L-F oscillator
operates at its fastest setting. When set to 1111b, the L-F oscillator operates at its slowest setting. The
effects of changing the OSCLF bits on the oscillator period are described in Equation 13.2.
Bits1-0: OSCLD[1:0]: Internal L-F Oscillator Divider Select.
00: Divide by 8 selected.
01: Divide by 4 selected.
10: Divide by 2 selected.
11: Divide by 1 selected.
R/W R R/W R/W R/W R/W R/W R/W Reset Value
OSCLEN OSCLRDY OSCLF3 OSCLF2 OSCLF1 OSCLF0 OSCLD1 OSCLD0 00xxxx00
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xE3
Equation 13.2. Typical Change in Internal L-F Oscillator Period with OSCLF Bits
∆T 0.03
1
f
BASE
-------------
∆OSCLF××≅