Specifications

C8051F330/1
Rev. 1.1 107
Figure 13.2. OSCICL: Internal H-F Oscillator Calibration Register
Bit7: UNUSED. Read = 0. Write = don’t care.
Bits 6-0: OSCICL: Internal Oscillator Calibration Register.
This register determines the internal oscillator period as per Equation 13.1. The reset value for
OSCICL defines the internal oscillator base frequency. On C8051F330/1 devices, the reset value is
factory calibrated to generate an internal oscillator frequency of 24.5 MHz.
R R/W R/W R/W R/W R/W R/W R/W Reset Value
Var iab le
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xB3
Figure 13.3. OSCICN: Internal H-F Oscillator Control Register
Bit7: IOSCEN: Internal H-F Oscillator Enable Bit.
0: Internal H-F Oscillator Disabled.
1: Internal H-F Oscillator Enabled.
Bit6: IFRDY: Internal H-F Oscillator Frequency Ready Flag.
0: Internal H-F Oscillator is not running at programmed frequency.
1: Internal H-F Oscillator is running at programmed frequency.
Bits5-2: UNUSED. Read = 0000b, Write = don't care.
Bits1-0: IFCN1-0: Internal H-F Oscillator Frequency Control Bits.
00: SYSCLK derived from Internal H-F Oscillator divided by 8.
01: SYSCLK derived from Internal H-F Oscillator divided by 4.
10: SYSCLK derived from Internal H-F Oscillator divided by 2.
11: SYSCLK derived from Internal H-F Oscillator divided by 1.
R/W R R R R R R/W R/W Reset Value
IOSCEN IFRDY - - - - IFCN1 IFCN0 11000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xB2