Specifications

C8051F330/1
106 Rev. 1.1
Electrical specifications for the precision internal oscillator are given in Table 13.1 on page 112. Note that the system
clock may be derived from the programmed internal oscillator divided by 1, 2, 4, or 8, as defined by the IFCN bits in
register OSCICN. The divide value defaults to 8 following a reset.
13.1.1. Programming the Internal H-F Oscillator on C8051F310/1 Devices
The OSCICL reset value is factory calibrated to result in a 24.5 MHz internal oscillator with a ±2% accuracy. Note
that the calibrated reset value of OSCICL may vary from device-to-device. Software should read and adjust the
value of OSCICL according to
Equation 13.1 to obtain the desired frequency. The example below shows how to
obtain a 20 MHz internal oscillator frequency.
Important Note: that if the sum of the reset value of OSCICL and ∆OSCICL is greater than 128 or less than 0, then
the device will not be capable of producing the desired frequency.
f
BASE
is the internal oscillator reset frequency; T
BASE
is the reset oscillator period.
f
DES
is the desired internal oscillator frequency; T
DES
is the desired oscillator period.
The required change in period (∆T
DES
) is the difference between the base period and the desired period.
Using Equation 13.1 and the above calculations, find ∆OSCICL:
∆OSCICL is rounded to the nearest integer (45) and added to the reset value of register OSCICL.
The resulting internal oscillator frequency is:
f
BASE
24500000Hz=
T
BASE
1
24500000
------------------------
s=
f
DES
20000000Hz=
T
DES
1
20000000
------------------------
s=
∆T
DES
1
20000000
------------------------
1
24500000
------------------------– 9.18 10
9–
× s==
9.18 10
9–
× 0.005
1
f
BASE
-------------
∆OSCICL××=
∆OSCICL 45=
f
OSC
20000000Hz=