Specifications

C8051F330/1
10 Rev. 1.1
Figure 15.8. Typical Master Transmitter Sequence...............................................................139
Figure 15.9. Typical Master Receiver Sequence ...................................................................140
Figure 15.10. Typical Slave Receiver Sequence ...................................................................141
Figure 15.11. Typical Slave Transmitter Sequence...............................................................142
Table 15.4. SMBus Status Decoding....................................................................................143
16. UART0
Figure 16.1. UART0 Block Diagram.....................................................................................145
Figure 16.2. UART0 Baud Rate Logic ..................................................................................146
Figure 16.3. UART Interconnect Diagram ............................................................................147
Figure 16.4. 8-Bit UART Timing Diagram ...........................................................................147
Figure 16.5. 9-Bit UART Timing Diagram ...........................................................................148
Figure 16.6. UART Multi-Processor Mode Interconnect Diagram .......................................149
Figure 16.7. SCON0: Serial Port 0 Control Register.............................................................150
Figure 16.8. SBUF0: Serial (UART0) Port Data Buffer Register .........................................151
Table 16.1. Timer Settings for Standard Baud Rates Using The Internal Oscillator ...........152
Table 16.2. Timer Settings for Standard Baud Rates Using an External Oscillator.............152
Table 16.3. Timer Settings for Standard Baud Rates Using an External Oscillator.............153
Table 16.4. Timer Settings for Standard Baud Rates Using an External Oscillator.............153
Table 16.5. Timer Settings for Standard Baud Rates Using an External Oscillator.............154
Table 16.6. Timer Settings for Standard Baud Rates Using an External Oscillator.............154
17. ENHANCED SERIAL PERIPHERAL INTERFACE (SPI0)
Figure 17.1. SPI Block Diagram............................................................................................155
Figure 17.2. Multiple-Master Mode Connection Diagram ....................................................158
Figure 17.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram ...158
Figure 17.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram ....158
Figure 17.5. Master Mode Data/Clock Timing......................................................................160
Figure 17.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................................161
Figure 17.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................................161
Figure 17.8. SPI0CFG: SPI0 Configuration Register............................................................162
Figure 17.9. SPI0CN: SPI0 Control Register ........................................................................163
Figure 17.10. SPI0CKR: SPI0 Clock Rate Register..............................................................164
Figure 17.11. SPI0DAT: SPI0 Data Register ........................................................................165
Figure 17.12. SPI Master Timing (CKPHA = 0)...................................................................166
Figure 17.13. SPI Master Timing (CKPHA = 1)...................................................................166
Figure 17.14. SPI Slave Timing (CKPHA = 0) .....................................................................167
Figure 17.15. SPI Slave Timing (CKPHA = 1) .....................................................................167
Table 17.1. SPI Slave Timing Parameters............................................................................168
18. TIMERS
Figure 18.1. T0 Mode 0 Block Diagram................................................................................170
Figure 18.2. T0 Mode 2 Block Diagram................................................................................171
Figure 18.3. T0 Mode 3 Block Diagram................................................................................172
Figure 18.4. TCON: Timer Control Register.........................................................................173
Figure 18.5. TMOD: Timer Mode Register...........................................................................174
Figure 18.6. CKCON: Clock Control Register......................................................................175
Figure 18.7. TL0: Timer 0 Low Byte ....................................................................................176