User`s guide

Si5365/66-EVB
Si5367/68-EVB
Rev. 0.4 5
For a differential external reference, connect the balanced input signals to J1 and J2. For single-ended operation,
connect the input signal to J1 and disconnect J2.
R51 is provided so that a different termination scheme can be used. If R51 is populated, then remove R52 and R24.
5.4. CPLD
This CPLD is required for the MCU to control the Si536x over a flexible 1.8 or 2.5 V V
DD
. The CPLD provides two
main functions: it translates the voltage level from 3.3 V (the MCU voltage) to the Si536x voltage (either 1.8 or
2.5 V). The MCU communicates to the CPLD with the SPI signals SS_CPLD_B (slave select), MISO (master in,
slave out), MOSI (master out, slave in) and SCLK. The MCU can talk to CPLD-resident registers that are
connected to pins that control the Si536x's pins, mainly for pin control mode. When the MCU wishes to access a
Si536x register, the SPI signals are passed through the CPLD, while being level translated, to the Si536x. The
CPLD is an EE device that is retains its code that is loaded through the JTAG port (J32). The core of the CPLD
runs at 1.8 V, which is provided by voltage regulator U4. The CPLD also logically connects many of the LEDs to the
appropriate Si536x pins.
Figure 3. SPI Mode Serial Data Flow
Table 2. Reference Input Mode
Mode
Xtal
1
38.88 MHz Ext Ref
2
Wide Band
Input 1
NC
3
J1 NC
Input 2
NC J2 NC
C39
NOPOP
4
install install
C22
NOPOP install NOPOP
R50
NOPOP NOPOP install
R28
install NOPOP NOPOP
RATE0
M—H
RATE1
M—H
Notes:
1. Xtal is 114.285 MHz 3rd overtone.
2. For external reference frequencies and RATE pin settings, see the
Any-Rate Precision Clock Family Reference Manual.
3. NC—no connect.
4. NOPOP—do not install this component.
MCU CPLD Si5367, Si5368
SS_CPLD_B
SCLK
MOSI
MISO
SS_B
SCLK
SDI
SDO
DUT_PWR
+3.3 V