Datasheet

Si5351A/B/C-B
Rev. 1.0 7
Table 6. Output Clock Characteristics
(V
DD
= 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Frequency Range
1
F
CLK
0.0025 — 200 MHz
Load Capacitance C
L
——15pF
Duty Cycle DC
F
CLK
< 160 MHz, Measured
at V
DD
/2
45 50 55 %
F
CLK
> 160 MHz, Measured
at V
DD
/2
40 50 60 %
Rise/Fall Time
t
r
20%–80%, C
L
=5pF,
Default high drive strength
—11.5ns
t
f
—11.5ns
Output High Voltage V
OH
C
L
=5pF
V
DD
– 0.6 — — V
Output Low Voltage V
OL
——0.6V
Period Jitter
2,3
J
PER
20-QFN, 4 outputs running,
1 per VDDO
—4095
ps, pk-
pk
10-MSOP or 20-QFN,
all outputs running
— 70 155
ps, pk-
pk
Cycle-to-Cycle Jitter
2,3
J
CC
20-QFN, 4 outputs running,
1 per VDDO
—5090ps, pk
10-MSOP or 20-QFN,
all outputs running
— 70 150 ps, pk
Period Jitter VCXO
2,3
J
PER_VCXO
20-QFN, 4 outputs running,
1 per VDDO
—5095
ps, pk-
pk
10-MSOP or 20-QFN,
all outputs running
— 70 155
ps, pk-
pk
Cycle-to-Cycle Jitter
VCXO
2,3
J
CC_VCXO
20-QFN, 4 outputs running,
1 per VDDO
—5090ps, pk
10-MSOP or 20-QFN,
all outputs running
— 70 150 ps, pk
Notes:
1. Only two unique frequencies above 112.5 MHz can be simultaneously output.
2. Measured over 10K cycles. Jitter is only specified at the default high drive strength (50  output impedance).
3. Jitter is highly dependent on device frequency configuration. Specifications represent a “worst case, real world”
frequency plan; actual performance may be substantially better. Three-output 10 MSOP package measured with clock
outputs of 74.25, 24.576, and 48 MHz. Eight-output 20 QFN package measured with clock outputs of 33.333, 74.25,
27, 24.576, 22.5792, 28.322, 125, and 48 MHz.