Datasheet
Si5351A/B/C-B
16 Rev. 1.0
4. I
2
C Interface
Many of the functions and features of the Si5351 are controlled by reading and writing to the RAM space using the
I
2
C interface. The following is a list of the common features that are controllable through the I
2
C interface. For a
complete listing of available I
2
C registers and programming steps, please see “AN619: Manually Generating an
Si5351 Register Map.”
Read Status Indicators
Crystal Reference Loss of signal, LOS_XTAL, reg0[3]
CLKIN Loss of signal, LOS_CLKIN, reg0[4]
PLLA and/or PLLB Loss of lock, LOL_A or LOL_B, reg0[6:5]
Configuration of multiplication and divider values for the PLLs, MultiSynth dividers
Configuration of the Spread Spectrum profile (down or center spread, modulation percentage)
Control of the cross point switch selection for each of the PLLs and MultiSynth dividers
Set output clock options
Enable/disable for each clock output
Invert/non-invert for each clock output
Output divider values (2
n
, n=1.. 7)
Output state when disabled (stop hi, stop low, Hi-Z)
Output phase offset
The I
2
C interface operates in slave mode with 7-bit addressing and can operate in Standard-Mode (100 kbps) or
Fast-Mode (400 kbps) and supports burst data transfer with auto address increments.
The I
2
C bus consists of a bidirectional serial data line (SDA) and a serial clock input (SCL) as shown in Figure 7.
Both the SDA and SCL pins must be connected to the VDD supply via an external pull-up as recommended by the
I
2
C specification.
Figure 7. I
2
C and Control Signals
The 7-bit device (slave) address of the Si5351 consist of a 6-bit fixed address plus a user selectable LSB bit as
shown in Figure 8. The LSB bit is selectable as 0 or 1 using the optional A0 pin which is useful for applications that
require more than one Si5351 on a single I
2
C bus.
Figure 8. Si5351 I
2
C Slave Address
SCL
VDD
SDA
I
2
C Bus
INTR
A0
I
2
C Address Select:
Pull-up to VDD (A0 = 1)
Pull-down to GND (A0 = 0)
Si5351
>1k
>
1k
4.7 k
Slave Address
1 1 0 0 0 0 0/1
A0
0123456