Datasheet

Si5351A/B/C-B
12 Rev. 1.0
3. Functional Description
The Si5351 is a versatile I
2
C programmable clock generator that is ideally suited for replacing crystals, crystal
oscillators, VCXOs, PLLs, and buffers. A block diagram showing the general architecture of the Si5351 is shown in
Figure 3. The device consists of an input stage, two synthesis stages, and an output stage.
The input stage accepts an external crystal (XTAL), a control voltage input (VC), or a clock input (CLKIN)
depending on the version of the device (A/B/C). The first stage of synthesis multiplies the input frequencies to an
high-frequency intermediate clock, while the second stage of synthesis uses high resolution MultiSynth fractional
dividers to generate the desired output frequencies. Additional integer division is provided at the output stage for
generating output frequencies as low as 2.5 kHz. Crosspoint switches at each of the synthesis stages allows total
flexibility in routing any of the inputs to any of the outputs.
Because of this high resolution and flexible synthesis architecture, the Si5351 is capable of generating
synchronous or free-running non-integer related clock frequencies at each of its outputs, enabling one device to
synthesize clocks for multiple clock domains in a design.
Figure 3. Si5351 Block Diagram
Input
Stage
Synthesis
Stage 1
PLL B
(VCXO)
PLL A
(SSC)
VC
VCXO
XA
XB
OSC
XTAL
CLKIN
Div
Multi
Synth
0
Multi
Synth
1
Multi
Synth
2
Multi
Synth
3
Multi
Synth
4
Multi
Synth
5
Multi
Synth
6
Multi
Synth
7
Synthesis
Stage 2
R0
R1
R2
R3
R4
R5
R6
R7
Output
Stage
CLK0
CLK1
VDDOA
CLK2
CLK3
VDDOB
CLK4
CLK5
VDDOC
CLK6
CLK7
VDDOD