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Si5351A/B/C-B

C-PROGRAMMABLE ANY-FREQUENCY CMOS CLOCK

GENERATOR + VCXO

Features

Applications

Description

The Si5351 is an I

C configurable clock generator that is ideally suited for replacing

crystals, crystal oscillators, VCXOs, phase-locked loops (PLLs), and fanout buffers in

cost-sensitive applications. Based on a PLL/VCXO + high resolution MultiSynth fractional

divider architecture, the Si5351 can generate any frequency up to 200 MHz on each of its

outputs with 0 ppm error. Three versions of the Si5351 are available to meet a wide

variety of applications. The Si5351A generates up to 8 free-running clocks using an

internal oscillator for replacing crystals and crystal oscillators. The Si5351B adds an

internal VCXO and provides the flexibility to replace both free-running clocks and

synchronous clocks. It eliminates the need for higher cost, custom pullable crystals while

providing reliable operation over a wide tuning range. The Si5351C offers the same

flexibility but synchronizes to an external reference clock (CLKIN).

Functional Block Diagram

 www.silabs.com/custom-timing

 Generates up to 8 non-integer-related

frequencies from 2.5 kHz to 200 MHz

 I

C user definable configuration

 Exact frequency synthesis at each output

(0 ppm error)

 Highly linear VCXO

 Optional clock input (CLKIN)

 Low output period jitter: < 70 ps pp, typ

 Configurable spread spectrum selectable

at each output

 Operates from a low-cost, fixed frequency

crystal: 25 or 27 MHz

 Supports static phase offset

 Programmable rise/fall time control

 Glitchless frequency changes

 Separate voltage supply pins provide

level translation:

Core VDD: 2.5 or 3.3 V

Output VDDO: 1.8, 2.5, or 3.3 V

 Excellent PSRR eliminates external

power supply filtering

 Very low power consumption

 Adjustable output delay

 Available in 2 packages types:

 10-MSOP: 3 outputs

 20-QFN (4x4 mm): 8 outputs

 PCIE Gen 1 compatible

 Supports HCSL compatible swing

 HDTV, DVD/Blu-ray, set-top box

 Audio/video equipment, gaming

 Printers, scanners, projectors

 Handheld Instrumentation

 Residential gateways

 Networking/communication

 Servers, storage

 XO replacement

CLK0

CLK1

VDDOA

CLK2

CLK3

VDDOB

CLK4

CLK5

VDDOC

CLK6

CLK7

VDDOD

MultiSynth

PLL

OSC

CLKIN

SCL

SDA

Control

Logic

INTR

OEB

Si5351C (20-QFN)

OSC

PLL

VCXO

CLK0

CLK1

VDDOA

CLK2

CLK3

VDDOB

CLK4

CLK5

VDDOC

CLK6

CLK7

VDDOD

MultiSynth

SCL

SDA

Control

Logic

OEB

SSEN

Si5351B (20-QFN)

Ordering Information:

See page 29

10-MSOP

20-QFN

Summary of content (41 pages)

PAGE 1
Si5351A/B/C-B I 2 C - P R O G R A M M A B L E A NY -F R E Q U E N C Y C M O S C LO CK G EN ER ATO R + V C X O Features            www.silabs.com/custom-timing Generates up to 8 non-integer-related frequencies from 2.
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Si5351A/B/C-B Table 1.
PAGE 3
Si5351A/B/C-B TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1. Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Si5351A/B/C-B 14.4. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 4 Rev. 1.
PAGE 5
Si5351A/B/C-B 1. Electrical Specifications Table 2. Recommended Operating Conditions Parameter Symbol Ambient Temperature TA Core Supply Voltage VDD Output Buffer Voltage Test Condition VDDOx Min Typ Max Unit –40 25 85 °C 3.0 3.3 3.60 V 2.25 2.5 2.75 V 1.71 1.8 1.89 V 2.25 2.5 2.75 V 3.0 3.3 3.60 V Notes:All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
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Si5351A/B/C-B Table 4. AC Characteristics (VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Power-up Time TRDY From VDD = VDDmin to valid output clock, CL = 5 pF, fCLKn > 1 MHz — 2 10 ms Power-up Time, PLL Bypass Mode TBYP From VDD = VDDmin to valid output clock, CL = 5 pF, fCLKn > 1 MHz — 0.
PAGE 7
Si5351A/B/C-B Table 6. Output Clock Characteristics (VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Frequency Range1 FCLK 0.0025 — 200 MHz Load Capacitance CL — — 15 pF FCLK < 160 MHz, Measured at VDD/2 45 50 55 % FCLK > 160 MHz, Measured at VDD/2 40 50 60 % — 1 1.5 ns — 1 1.5 ns VDD – 0.6 — — V — — 0.
PAGE 8
Si5351A/B/C-B Table 7. Crystal Requirements1,2 Parameter Symbol Min Typ Max Unit Crystal Frequency fXTAL 25 — 27 MHz Load Capacitance CL 6 — 12 pF rESR — — 150  dL 100 — — µW Equivalent Series Resistance Crystal Max Drive Level Notes: 1. Crystals which require load capacitances of 6, 8, or 10 pF should use the device’s internal load capacitance for optimum performance. See register 183 bits 7:6.
PAGE 9
Si5351A/B/C-B Table 9. Thermal Characteristics Parameter Symbol Test Condition Thermal Resistance Junction to Ambient JA Still Air Thermal Resistance Junction to Case JC Still Air Package Value Unit 10-MSOP 131 °C/W 20-QFN 119 °C/W 20-QFN 16 °C/W Value Unit –0.5 to 3.8 V Table 10. Absolute Maximum Ratings1 Parameter DC Supply Voltage Symbol Test Condition VDD_max VIN_CLKIN CLKIN, SCL, SDA –0.5 to 3.8 V VIN_VC VC –0.5 to (VDD+0.3) V VIN_XA/B Pins XA, XB –0.5 to 1.
PAGE 10
Si5351A/B/C-B 2.
PAGE 11
Si5351A/B/C-B VDD XA OSC PLL XB VCXO VC SDA I2C SCL Interface OEB Control Logic SSEN Si5351B VDDOA MultiSynth 0 R0 MultiSynth 1 R1 MultiSynth 2 R2 MultiSynth 3 R3 MultiSynth 4 R4 MultiSynth 5 R5 MultiSynth 6 R6 MultiSynth 7 R7 VDDOB SCL INTR OEB Control Logic CLK5 CLK6 CLK7 VDDOA R0 MultiSynth 1 R1 MultiSynth 2 R2 MultiSynth 3 R3 MultiSynth 4 R4 MultiSynth 5 R5 MultiSynth 6 R6 MultiSynth 7 R7 PLL B I2C Interface CLK4 VDDOD MultiSynth 0 PLL A SDA CLK3
PAGE 12
Si5351A/B/C-B 3. Functional Description The Si5351 is a versatile I2C programmable clock generator that is ideally suited for replacing crystals, crystal oscillators, VCXOs, PLLs, and buffers. A block diagram showing the general architecture of the Si5351 is shown in Figure 3. The device consists of an input stage, two synthesis stages, and an output stage.
PAGE 13
Si5351A/B/C-B 3.1. Input Stage 3.1.1. Crystal Inputs (XA, XB) The Si5351 uses a fixed-frequency standard AT-cut crystal as a reference to the internal oscillator. The output of the oscillator can be used to provide a free-running reference to one or both of the PLLs for generating asynchronous clocks. The output frequency of the oscillator will operate at the crystal frequency, either 25 MHz or 27 MHz. The crystal is also used as a reference to the VCXO to help maintain its frequency accuracy.
PAGE 14
Si5351A/B/C-B 3.2. Synthesis Stages The Si5351 uses two stages of synthesis to generate its final output clocks. The first stage uses PLLs to multiply the lower frequency input references to a high-frequency intermediate clock. The second stage uses highresolution MultiSynth fractional dividers to generate the required output frequencies. Only two unique frequencies above 112.5 MHz can be simultaneously output. For example, 125 MHz (CLK0), 130 MHz (CLK1), and 150 MHz (CLKx) is not allowed.
PAGE 15
Si5351A/B/C-B 3.3. Output Stage An additional level of division (R) is available at the output stage for generating clocks as low as 2.5 kHz. All output drivers generate CMOS level outputs with separate output voltage supply pins (VDDOx) allowing a different voltage signal level (1.8, 2.5, or 3.3 V) at each of the four 2-output banks. 3.4. Spread Spectrum Spread spectrum can be enabled on any of the clock outputs that use PLLA as its reference.
PAGE 16
Si5351A/B/C-B 4. I2C Interface Many of the functions and features of the Si5351 are controlled by reading and writing to the RAM space using the I2C interface. The following is a list of the common features that are controllable through the I2C interface. For a complete listing of available I2C registers and programming steps, please see “AN619: Manually Generating an Si5351 Register Map.
PAGE 17
Si5351A/B/C-B Data is transferred MSB first in 8-bit words as specified by the I2C specification. A write command consists of a 7bit device (slave) address + a write bit, an 8-bit register address, and 8 bits of data as shown in Figure 9. A write burst operation is also shown where every additional data word is written using to an auto-incremented address.
PAGE 18
Si5351A/B/C-B 5. Configuring the Si5351 The Si5351 is a highly flexible clock generator which is entirely configurable through its I2C interface. The device’s default configuration is stored in non-volatile memory (NVM) as shown in Figure 11. The NVM is a one time programmable memory (OTP) which can store a custom user configuration at power-up. This is a useful feature for applications that need a clock present at power-up (e.g., for providing a clock to a processor).
PAGE 19
Si5351A/B/C-B Disable Outputs Set CLKx_DIS high; Reg. 3 = 0xFF Powerdown all output drivers Reg. 16, 17, 18, 19, 20, 21, 22, 23 = 0x80 Set interrupt masks (see register 2 description) Register Map Use ClockBuilder Desktop v3.1 or later Write new configuration to device using the contents of the register map generated by ClockBuilder Desktop. This step also powers up the output drivers. 149-170 and 183) (Registers 15-92 ,and 149-170) Apply PLLA and PLLB soft reset Reg.
PAGE 20
Si5351A/B/C-B 5.2. Si5351 Application Examples The Si5351 is a versatile clock generator which serves a wide variety of applications. The following examples show how it can be used to replace crystals, crystal oscillators, VCXOs, and PLLs. 5.3. Replacing Crystals and Crystal Oscillators Using an inexpensive external crystal, the Si5351A can generate up to 8 different free-running clock frequencies for replacing crystals and crystal oscillators.
PAGE 21
Si5351A/B/C-B 5.5. Replacing Crystals, Crystal Oscillators, and PLLs The Si5351C generates synchronous clocks for applications that require a fully integrated PLL instead of a VCXO. Because of its dual PLL architecture, the Si5351C is capable of generating both synchronous and free-running clocks. An example is shown in Figure 15.
PAGE 22
Si5351A/B/C-B 5.7. HCSL Compatible Outputs The Si5351 can be configured to support HCSL compatible swing when the VDDO of the output pair of interest is set to 2.5 V (i.e., VDDOA must be 2.5 V when using CLK0/1; VDDOB must be 2.5 V for CLK2/3 and so on). The circuit in the figure below must be applied to each of the two clocks used, and one of the clocks in the pair must also be inverted to generate a differential pair. See register setting CLKx_INV.
PAGE 23
Si5351A/B/C-B 6. Design Considerations The Si5351 is a self-contained clock generator that requires very few external components. The following general guidelines are recommended to ensure optimum performance. Refer to “AN554: Si5350/51 PCB Layout Guide” for additional layout recommendations. 6.1. Power Supply Decoupling/Filtering The Si5351 has built-in power supply filtering circuitry and extensive internal Low Drop Out (LDO) voltage regulators to help minimize the number of external bypass components.
PAGE 24
Si5351A/B/C-B 7. Register Map Summary For many applications, the Si5351's register values are easily configured using ClockBuilder Desktop software. However, for customers interested in using the Si5351 in operating modes beyond the capabilities available with ClockBuilder™, refer to “AN619: Manually Generating an Si5351 Register Map” for a detailed description of the Si5351 registers and their usage. 8.
PAGE 25
Si5351A/B/C-B 9. Si5351 Pin Descriptions XA 1 XB 2 A0 3 SCL 4 16 CLK6 17 CLK5 18 VDDOC 19 CLK4 20 VDD 9.1. Si5351A 20-pin QFN 15 CLK7 14 VDDOD GND PAD 13 CLK0 12 CLK1 9 CLK2 VDDOB 10 7 8 OEB SSEN CLK3 11 VDDOA 6 SDA 5 Figure 19. Si5351A 20-QFN Top View Table 11. Si5351A Pin Descriptions Pin Name Pin Number Pin Type1 XA 1 I Input pin for external crystal. XB 2 I Input pin for external crystal. CLK0 13 O Output clock 0. CLK1 12 O Output clock 1.
PAGE 26
Si5351A/B/C-B 16 CLK6 17 CLK5 18 VDDOC 19 CLK4 20 VDD 9.2. Si5351B 20-Pin QFN XA 1 15 XB 2 14 VC 3 SCL 4 12 SDA 5 11 GND PAD 7 8 9 OEB CLK3 CLK2 VDDOD CLK0 CLK1 VDDOA VDDOB 10 6 SSEN 13 CLK7 Figure 20. Si5351B 20-QFN Top View* Table 12.
PAGE 27
Si5351A/B/C-B XA 1 XB 2 16 CLK6 17 CLK5 18 VDDOC 19 CLK4 20 VDD 9.3. Si5351C 20-Pin QFN GND PAD 15 CLK7 14 VDDOD 13 CLK0 VDDOA VDDOB 10 11 9 5 CLK2 SDA 8 CLK1 CLK3 12 7 4 OEB SCL 6 3 CLKIN INTR Table 13. Si5351C Pin Descriptions Pin Name Pin Number Pin Type1 Function 20-QFN XA 1 I Input pin for external crystal. XB 2 I Input pin for external crystal. CLK0 13 O Output clock 0. CLK1 12 O Output clock 1. CLK2 9 O Output clock 2.
PAGE 28
Si5351A/B/C-B 9.4. Si5351A 10-Pin MSOP VDD 1 10 CLK0 XA 2 9 CLK1 XB 3 8 GND SCL 4 7 VDDO SDA 5 6 CLK2 Figure 21. Si5351A 10-MSOP Top View Table 14. Si5351A 10-MSOP Pin Descriptions Pin Name Pin Number Pin Type* Function 10-MSOP XA 2 I Input pin for external crystal. XB 3 I Input pin for external crystal. CLK0 10 O Output clock 0. CLK1 9 O Output clock 1. CLK2 6 O Output clock 2. SCL 4 I Serial clock input for the I2C bus.
PAGE 29
Si5351A/B/C-B 10. Ordering Information Factory pre-programmed Si5351 devices (e.g., with bootup frequencies) can be requested using the ClockBuilder web-based utility available at: www.silabs.com/ClockBuilder. A unique part number is assigned to each custom configuration as indicated in Figure 22. Blank, un-programmed Si5351 devices (with no boot-up frequency) do not contain a custom code. Figure 22.
PAGE 30
Si5351A/B/C-B 11. Package Outlines Figure 24 shows the package details for the Si5351 in a 20-QFN package. Table 15 lists the values for the dimensions shown in the illustration. Seating Plane 11.1. 20-pin QFN C D2 B D A D2/2 A1 L E E2 E2/2 b A e Figure 24. 20-pin QFN Package Drawing 30 Rev. 1.
PAGE 31
Si5351A/B/C-B Table 15. Package Dimensions Dimension A Min 0.80 Nom 0.85 Max 0.90 A1 0.00 — 0.05 b D D2 e E E2 L 0.20 0.30 2.65 0.35 0.25 4.00 BSC 2.70 0.50 BSC 4.00 BSC 2.70 0.40 2.75 0.45 aaa — — 0.10 bbb — — 0.10 ccc — — 0.08 ddd — — 0.10 2.65 2.75 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC Outline MO-220, variation VGGD-5. 4.
PAGE 32
Si5351A/B/C-B 12. Land Pattern: 20-Pin QFN Figure 25 shows the recommended land pattern details for the Si5351 in a 20-Pin QFN package. Table 16 lists the values for the dimensions shown in the illustration. Figure 25. 20-Pin QFN Land Pattern 32 Rev. 1.
PAGE 33
Si5351A/B/C-B Table 16. PCB Land Pattern Dimensions Symbol Millimeters C1 4.0 C2 4.0 E 0.50 BSC X1 0.30 X2 2.70 Y1 0.80 Y2 2.70 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This land pattern design is based on IPC7351 guidelines. Solder Mask Design 3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 4.
PAGE 34
Si5351A/B/C-B 12.1. 10-Pin MSOP Package Outline Figure 26 illustrates the package details for the Si5351 in a 10-pin MSOP package. Table 17 lists the values for the dimensions shown in the illustration. Figure 26. 10-pin MSOP Package Drawing 34 Rev. 1.
PAGE 35
Si5351A/B/C-B Table 17. 10-MSOP Package Dimensions Dimension A A1 A2 b c D E E1 e L L2 q aaa bbb ccc ddd Min — 0.00 0.75 0.17 0.08 Nom — — 0.85 — — 3.00 BSC 4.90 BSC 3.00 BSC 0.50 BSC 0.60 0.25 BSC — — — — — 0.40 0 — — — — Max 1.10 0.15 0.95 0.33 0.23 0.80 8 0.20 0.25 0.10 0.08 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation C 4.
PAGE 36
Si5351A/B/C-B 13. Land Pattern: 10-Pin MSOP Figure 27 shows the recommended land pattern details for the Si5351 in a 10-Pin MSOP package. Table 18 lists the values for the dimensions shown in the illustration. Figure 27. 10-Pin MSOP Land Pattern 36 Rev. 1.
PAGE 37
Si5351A/B/C-B Table 18. PCB Land Pattern Dimensions Symbol Millimeters Min Max C1 4.40 REF E 0.50 BSC G1 3.00 — X1 — 0.30 Y1 Z1 1.40 REF — 5.80 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ASME Y14.5M-1994. 3. This Land Pattern Design is based on the IPC-7351 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC).
PAGE 38
Si5351A/B/C-B 14. Top Marking 14.1. 20-Pin QFN Top Marking Figure 28. 20-Pin QFN Top Marking 14.2. Top Marking Explanation Mark Method: Laser Pin 1 Mark: Filled Circle = 0.50 mm Diameter (Bottom-Left Corner) Font Size: 0.60 mm (24 mils) Line 1 Mark Format Device Part Number Si5351 Line 2 Mark Format: TTTTTT = Mfg Code* Manufacturing Code from the Assembly Purchase Order Form. Line 3 Mark Format: YY = Year WW = Work Week Assigned by the Assembly House.
PAGE 39
Si5351A/B/C-B 14.3. 10-Pin MSOP Top Marking Figure 29. 10-Pin MSOP Top Marking 14.4. Top Marking Explanation Mark Method: Laser Pin 1 Mark: Mold Dimple (Bottom-Left Corner) Font Size: 0.60 mm (24 mils) Line 1 Mark Format Device Part Number Si5351 Line 2 Mark Format: TTTT = Mfg Code* Line 2 from the “Markings” section of the Assembly Purchase Order form. Line 3 Mark Format: YWW = Date Code Assigned by the Assembly House.
PAGE 40
Si5351A/B/C-B DOCUMENT CHANGE LIST Revision 0.75 to Revision 1.0          40 Extended frequency range from 8 MHz-160 MHz to 2.5 kHz-200 MHz. Updated block diagrams for clarity. Added complete Si5350/1 family table, Table 1. Added top mark information. Added land pattern drawings. Added PowerUp Time, PLL Bypass mode, Table 4. Clarified Down Spread step sizes in Table 4. Updated max jitter specs (typ unchanged) in Table 6. Clarified power supply sequencing requirement, Section 6.2. Rev. 1.
PAGE 41
Si5351A/B/C-B CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request.