Specifications
Si2493
12 Rev. 1.3
EECLK/D5
DCD_/D4
ESC/D3
AOUT/INT_
TXD/WR_
RESET_
RXD/RD_
CTS_/CS_
D6
INT_/D0
RI_/D1
EESD/D2
CLKOUT/EECS_/A0
RTS_/D7
VDD
RING
TIP
No Ground Plane In DAA Section
External
crystal
option
Emissions option
Bias
Ring Detect/CID
Hookswitch
DC Term
Bypass
Refer to AN93 Appendix A for layout guidelines.
Please submit layout to Silicon Labs for review
prior to PCB fabrication.
Y1
12
FB2
R13
C41
C10
Z1
U2
QE
1
DCT
2
RX
3
IB
4
C1B
5
C2B
6
VREG
7
RNG1
8
DCT2
16
IGND
15
DCT3
14
QB
13
QE2
12
SC
11
VREG2
10
RNG2
9
R3
C51
C40
R9
C1
C2
+
C4
-+
D1
R4
R7
R10
R6
Q2
R8
R16
Q4
C9
C53
RV1
FB1
C50
C5
C7
C6
R15
C8
Q1
R5
U1
CLKIN/XTALI
1
XTALO
2
CLKOUT/EECS/A0
3
D6
4
VD3.3
5
GND
6
VDA
7
RTS/D7
8
VDB
19
GND
20
VD 3.3
21
C2A
13
C1A
14
ESC/D3
22
DCD/D4
23
EECLK/D5
24
CTS/CS
11
RXD/RD
9
TXD/WR
10
RESET
12
RI/D1
17
EESD/D2
18
AOUT/INT
15
INT/D0
16
Q3
C3
R11
R2
C52
Q5
R12
R1
Figure 7. Typical Si2493 Schematic with 24-pin System-Side Option