Specifications

AN93
90 Rev. 0.9
3.3.37. U6E (CK1)
U6E controls the clockout divider. Bits 15:13 and 7:0 are
reserved. U6E resets to 0x7F20 with a power-on or
manual reset. (See Table 58.)
Bits[12:8] (R1) make up the R1 clockout divider. An
81.92 MHz (Si2404/15) or 98.304 MHz (Si2434/57)
clock signal passes through a ÷(R
1
+1) circuit to derive
the CLKOUT signal on pin 3 of the Si2493/57/34/15/04.
If R1 = 00000
b
, CLKOUT is disabled. R1 is set at a
default value of 11111
b
resulting in
CLKOUT = 2.048 MHz (Si2434/57) or
CLKOUT = 2.048 MHz (Si2404/15). The CLKOUT
adjustment range (1 <
R1 < 30) is 2.64 MHz to
40.96 MHz for the Si2404/Si2415 and 3.17 MHz to
49.152 MHz for the Si2434/Si2457/Si2493.
3.3.38. U6F (PTME)
U6F contains the parallel port receive FIFO interrupt
timer and resets to 0x00FF.
Bits [15:8] are reserved and should not be written to any
value other than 0b.
Bits[7:0] set the period of an internal timer that is reset
whenever the parallel port receive FIFO (Parallel
Interface 0 register) is read. If the internal timer expires
with data in the RX FIFO, an interrupt is generated
regardless of the state of RXF (Parallel Interface 1
register, bit 7). This ensures that the host always
removes all receive data from the parallel port receive
FIFO even if RXF is not set.
3.3.39. U70 (IO0)
U70 controls escape and several indicator and detector
masks and provides several read-only status bits. (See
Table 60.) Bits 5, 6, 7, and 14 are reserved.
Bits 4:0 are read only, and bits 15 and 13:8 are read/
write. U70 resets to 0x2700 with a power-on or manual
reset.
Bit 15 (HES) = 0
b
(default) disables the hardware
escape pin (Si2493/57/34/15/04, pin 22 [ESC]).
Setting HES = 1
b
enables ESC. When ESC is enabled,
escape from the data mode to the command mode
occurs at the rising edge of the ESC pin. Multiple
escape options can be enabled simultaneously.
For example, U70[13] (TES) = 1
b
by default, which
enables the “+++” escape. If HES is also set
(HES = 1
b
), either escape method works. Additionally,
the 9th bit escape can also be enabled with the AT\B6
command or through autobaud.
Table 57. U6C Bit Map
Bit Name Function
15:8 LVS[7:0] Line Voltage Status.
Eight bit signed 2s complement number representing the on-hook and off-hook tip-ring voltage. Each bit
represents 1 V. Polarity of the voltage is represented by the MSB (sign bit). 0000_0000 = Measured volt-
age is < 3 V.
7:0 Reserved Read returns zero.
Table 58. U6E Bit Map
Bit Name Function
15:13 Reserved Do not modify.
12:8 R1 R1 CLKOUT Divider.
7:0 Reserved Read returns zero. (bit 5 returns 1) Do not modify.
Table 59. U6F Bit Map
Bit Name Function
15:8 Reserved Do not modify
7:0 PTMR Parallel Port Receive FIFO Interrupt Timer. PTMR (msec units)