Specifications

AN93
Rev. 0.9 61
WEL = write enable latch
WIP = write in progress
Table 26. EEPROM Status Register (Any Other Bits are Unused)
76543210
——————WELWIP
Table 27. EEPROM Commands
Instruction Name Instruction Format Description
READ 0000 0011 Read data from memory at address
WRITE 0000 0010 Write data to memory array beginning at address
WRDI 0000 0100 Clear write enable bit (disable write operation)
RDSR 0000 0101 Read status register
WRSR 0000 0001 Write status register
WREN 0000 0110 Set write enable bit (enable write operations)
Table 28. EEPROM Timing
Parameter Symbol Min. Typ. Max. Unit
EECLK period ECLK 1.0 — — µs
EESD input setup time EISU 100 — — ns
EESD input hold time EIH 100 — — ns
EESD output setup time* EOSU 500 — — ns
EESD output hold time* EOH 500 — — ns
EECS
asserted to EECLK positive edge ECSS 500 — — ns
EESD tristated before last falling EECLK edge during read
cycle. Last positive half of EECLK cycle is extended to provide
both 500 ns minimum EOH and 100 ns EESD before EECLK
falling edge.
EOZ 100 — — ns
EECS
disable time between accesses ECSW 500 — — ns
EECS
asserted after final EECLK edge ECSH 1 — — µs
*Note: EESD output at negative EECLK edge