Specifications

AN93
60 Rev. 0.9
may be allocated to the <commands> portion of the
EEPROM is limited to 1000 bytes.
Firmware upgrades may also be automatically loaded
into the Si2493/57/34/15/04 using the BOOT format.
Note that three <CR>’s must be the last three entries in
the EEPROM.
The Si2493/57/34/15/04 includes a simple three-wire
interface that may be directly connected to serial SPI
EEPROMs that are available from several different
manufacturers.
For example:
25LC080—25LC640 Microchip
AT25080—AT25640 Atmel
The EEPROM must be between 8192 and 65536 bits in
size and support the commands given in Table 27. The
EEPROM must also support 16-bit addressing
regardless of size, allow a minimum clock frequency of
1 MHz, and should assert its output on falling edges of
EECLK and latch input data on rising edges of EECLK.
A four-wire EEPROM (with separate serial input and
output data wires may be used with the input and output
pins connected to EESD so long as SDO is tristated on
the last falling edge of EECLK during a read cycle. All
data is sent to and from the EEPROM with the LSB first.
Figure 13 shows the connection diagram for the
EEPROM feature.
Figure 13. EEPROM Connection Diagram
SPI
EEPROM
HOST
Si2457/34/15/04
TELEPHONE
LINE
SO/SI
CS
EECS
SCLK
EESD
EECLK
Si3018/10