Specifications

AN93
172 Rev. 0.9
Table 110. Si2493/57/34/15/04/Si3008 Layout Checklist
3
# Layout Requirement
1
Place U1 and U3 so pins 9-16 of U1 are facing pins 1-4 of U3
2
Place U1, U3, C1 and C2 to provide minimum required creepage distance
3
Place R12 and R13 close to U1
4
Place C1 and C2 directly between U1 and U3, connect with short direct traces
5
Place R7, R8, R18, and R19 and C11 close to U2, keeping away from U3 pins 1 and 2
6
Provide large collector pads for heat sinking Q2 and Q3.
7
Use >15 mil trace widths in DAA section and >20 mil IGND trace widths
8
Place C3 directly across D1 and minimize IGND trace length
9
Place FB1, FB2, R15, R16, and RV1 close to the RJ-11 jack
10
Place C8 and C9 to minimize trace length to chassis ground
11
The traces from the RJ-11 through C8 and C9 to chassis ground must be short
12
Keep C8 and C9 away from C1 and C2 or place at 90 degrees
13
Use >20mil trace widths between RJ-11, FB1-2, R15, R16, RV1 C8 and C9
14
Match the routing from the RJ-11 to FB1 and FB2
15
Match traces from FB1, R7, C11 to U3 to those from FB2, R8, R18 to U3
16
There must be no digital ground or power plane in DAA area
17
Place C4 close to U2 and connect with very short direct traces
18
>5 mm creepage between any TNV and SELV component, pad or trace
19
Mark U1 pin 1 and U3 pin1
20
Allow space and mounting holes for fire enclosure if required
21
IGND plane does NOT extend under C3, D1, FB1-2, R15-16, C8-9 or RV1
22
All traces connecting C50, C51, C52 and U1 must be short and direct
23
The XTALI, Y1, XTALO loop must be minimized and routed on one layer
24
The Y1, C40, C41 loop must be minimized and routed on one layer
25
No traces can be routed through the Y1, C40, C41 loop
26
Space U2, Q1, Q2, Q3, R1, R2, and R10 for best thermal performance.
27
Size Q1, Q2, and Q3 collector pads to safely dissipate 0.15 W (see text).
28
Submit layout to Silicon Laboratories for review